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* fpga: Add Vivado project option to USRP FPGA buildsWade Fife2024-03-151-0/+1
* fpga: Add incremental to strategies for e3xx, n3xx, x3xxWade Fife2024-03-141-1/+4
* fpga: Update x3xx/e3xx RFNoC image core filesJavier Valenzuela2024-03-131-56/+56
* fpga: Fix RFNoC OOT Makefile inclusionWade Fife2023-07-261-0/+2
* FPGA: Synchronize X300 RX frontends on time changemichael-west2023-05-101-1/+2
* fpga: Update all RFNoC image core filesWade Fife2023-02-242-63/+76
* fpga: Update RFNoC YAML copyrightWade Fife2023-02-221-1/+1
* fpga: Add BUILD_BASE_DIR option to makefilesWade Fife2023-02-091-2/+5
* fpga: Add BUILD_SEED variableWade Fife2023-02-072-11/+24
* fpga: Require AR76780 for X3xx and E3xxWade Fife2022-09-231-0/+1
* fpga: e31x: Cleanup MTU parametersWade Fife2022-09-012-0/+7
* fpga: e31x: Add PROTOVER to eth_internalWade Fife2022-09-011-1/+3
* fpga: Fix target dependencies in Makefile.xxx.incWade Fife2022-08-291-4/+4
* fpga: e31x: Fix IP dependenciesWade Fife2022-08-291-7/+11
* fpga: e31x: Upgrade to Vivado 2021.1Sam O'Brien2022-08-255-89/+105
* fpga: Update makefiles to allow parallel FPGA buildsWade Fife2022-08-167-15/+42
* fpga: rfnoc: Remove rfnoc_version from target YAMLWade Fife2022-05-111-1/+0
* fpga: Update all RFNoC imagesWade Fife2022-03-313-33/+35
* rfnoc: Update device port names in image core YAMLWade Fife2022-03-311-24/+34
* fpga: Use PROTOVER and CHDR_W from RFNoC image builderWade Fife2022-03-293-5/+25
* fpga: e31x: Update DRAM IP simulationWade Fife2022-03-231-4/+22
* fpga: e31x: Fix DRAM traffic gen IP nameWade Fife2022-03-231-1/+1
* fpga: e31x: Add DRAM supportWade Fife2022-02-1015-99/+1499
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-301-0/+4
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-103-196/+261
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-081-2/+2
* fpga: e31x: Add OOT sources to Makefile.e31x.incWade Fife2020-11-131-0/+8
* fpga: e31x: Change image file to e310_rfnoc_image_coreWade Fife2020-09-093-5/+5
* fpga: e31x: Change RFNoC Ctrl clock to 40 MHzWade Fife2020-08-192-1/+3
* fpga: e31x: Fix timeout for timekeeper registersWade Fife2020-08-191-180/+278
* fpga: e310: Fix device in image core YAMLWade Fife2020-08-141-1/+1
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-241-1/+1
* fpga: rfnoc: Fix testbenches to run under ModelSimWade Fife2020-07-201-3/+4
* fpga: e31x: Add gitignore fileMartin Braun2020-07-181-0/+8
* e31x: Minor cleanup on top-level e31x.v moduleMartin Braun2020-07-182-15/+14
* e31x: Swap out liberio for internal ethernet in the idle imageRobertWalstab2020-07-181-2/+2
* e31x: fpga: connect device_idRobertWalstab2020-07-181-1/+5
* e31x: Swap out liberio for internal EthernetRobertWalstab2020-07-165-429/+522
* fpga: Update RFNOC_EDGE_TBL_FILE for CygwinWade Fife2020-06-121-1/+1
* fpga: e31x: Replace symbolic link for CygwinWade Fife2020-05-121-1/+1
* fpga: e31x: Update constraints to avoid timing issuesWade Fife2020-04-081-6/+6
* Merge FPGA repository back into UHD repositoryMartin Braun2020-01-2857-0/+41040
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