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* fpga: Add Vivado project option to USRP FPGA buildsWade Fife2024-03-151-0/+1
* fpga: n3xx: Rename BIST image coresWade Fife2024-03-159-6/+9
* fpga: Add incremental to strategies for e3xx, n3xx, x3xxWade Fife2024-03-141-1/+4
* n3xx: Add comments on clock_source=external,time_source=gpsdoDavid Raeman2024-02-211-1/+7
* fpga: n3xx: Add CE clockWade Fife2023-10-1812-658/+761
* fpga: Fix RFNoC OOT Makefile inclusionWade Fife2023-07-261-1/+2
* FPGA: Synchronize X300 RX frontends on time changemichael-west2023-05-101-1/+2
* fpga: Update all RFNoC image core filesWade Fife2023-02-2412-982/+1174
* fpga: Update RFNoC YAML copyrightWade Fife2023-02-226-6/+6
* fpga: Add BUILD_BASE_DIR option to makefilesWade Fife2023-02-091-2/+5
* fpga: Add BUILD_SEED variableWade Fife2023-02-072-15/+28
* fpga: Update copyrightmichael-west2023-01-191-0/+1
* FPGA: Restore FIR filter in rx_frontend_gen3michael-west2023-01-191-1/+1
* fpga: n3xx: Cleanup MTU parametersWade Fife2022-09-015-1/+26
* fpga: n3xx: Add PROTOVER to n3xx_mgt_wrapperWade Fife2022-09-011-0/+1
* fpga: n3xx: Remove unused USE_REPLAY parameterWade Fife2022-09-014-21/+10
* fpga: n3xx: Bump FPGA compat to 8.1Wade Fife2022-08-291-1/+1
* fpga: n3xx: Support advanced transport adapterWade Fife2022-08-295-306/+427
* fpga: Fix target dependencies in Makefile.xxx.incWade Fife2022-08-291-5/+5
* fpga: n3xx: Add BUFG to SPI output line to ease timingHumberto Jimenez2022-08-251-2/+12
* fpga: Use AR76780 patch for fir_compilerHumberto Jimenez2022-08-253-4/+5
* fpga: n3xx: Fix async clocks relationshipSam O'Brien2022-08-251-0/+2
* fpga: n3xx: Upgrade to Vivado 2021.1Sam O'Brien2022-08-2520-374/+1124
* fpga: Update makefiles to allow parallel FPGA buildsWade Fife2022-08-1622-53/+142
* fpga: rfnoc: Remove rfnoc_version from target YAMLWade Fife2022-05-116-6/+0
* fpga: Update all RFNoC imagesWade Fife2022-03-3112-248/+274
* rfnoc: Update device port names in image core YAMLWade Fife2022-03-316-295/+367
* fpga: n3xx: Add missing BIST image core headersWade Fife2022-03-296-45/+108
* fpga: Use PROTOVER and CHDR_W from RFNoC image builderWade Fife2022-03-295-13/+49
* fpga: n3xx: Fix clock frequency commentsWade Fife2022-03-261-2/+2
* Remove FSRU-related filesMartin Braun2022-02-221-1/+0
* fpga: n3xx: Fix DRAM FIFO address alignmentWade Fife2022-02-103-6/+6
* images: Update N32x CPLD manifestHumberto Jimenez2022-01-311-1/+1
* fpga: n3xx: rh: cpld: Refactor CPLD build processHumberto Jimenez2022-01-256-24/+119
* fpga: n3xx: Update synchronizer constraintWade Fife2021-09-131-3/+2
* fpga: Set default part for sim in setupenv.shWade Fife2021-08-301-0/+4
* N3xx: Fix White Rabbitmichael-west2021-08-041-0/+10
* fpga: Update testbenches to work in ModelSimWade Fife2021-06-172-6/+64
* fpga: Update rfnoc_image_core for all targetsWade Fife2021-06-109-3582/+3997
* fpga: Change RFNoC YAML version numbers to stringsWade Fife2021-06-086-12/+12
* fpga: Add Replay Block to RFNoC Core Imagemattprost2020-09-0310-145/+1402
* fpga: Update DRAM IO signaturesWade Fife2020-09-031-10/+10
* fpga: n3xx: Update AXI interconnect address rangeWade Fife2020-08-284-2928/+2217
* fpga: n3xx: Fix timeout for timekeeper registersWade Fife2020-08-193-195/+307
* n320: Double radio ingress buffer sizemattprost2020-08-122-8/+8
* fpga: n320: Add BIST (AA) image filessteviez2020-07-315-0/+1148
* fpga, mpm: Bump FPGA compat numberRobertWalstab2020-07-241-1/+1
* n32x: Swap out liberio for internal EthernetRobertWalstab2020-07-161-30/+138
* n3xx: Swap out liberio for internal EthernetRobertWalstab2020-07-164-1115/+1262
* fpga: n3xx: Fix White Rabbit imagesWade Fife2020-07-011-3/+19
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