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#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
# This pipeline is used to build FPGAs and run testbenches for PRs.
#
# See https://aka.ms/yaml for pipeline YAML documentation.
#
parameters:
- name: run_testbenches
type: boolean
displayName: Run Testbenches
default: true
- name: clean_ip_build
type: boolean
displayName: Clean IP Build
default: false
- name: num_ip_jobs
type: number
default: 5
displayName: Number of parallel IP jobs
- name: package_and_publish_images
type: boolean
displayName: Package & Publish Images
default: true
- name: package_access
type: string
values:
- 'Internal'
- 'files.ettus.com (Public)'
displayName: Published Package Access
default: 'Internal'
- name: build_x410
type: boolean
displayName: Build X410
default: true
- name: build_x440
type: boolean
displayName: Build X440
default: true
- name: x410_targets_matrix
type: object
displayName: X410 Targets
default:
X410_XG_100:
image_core: x410_200_rfnoc_image_core.yml
target_name: X410_XG_100
timeout: 720
max_attempts: 2
X410_UC_200:
image_core: x410_200_rfnoc_image_core.yml
target_name: X410_UC_200
timeout: 720
max_attempts: 2
X410_X4_200:
image_core: x410_200_rfnoc_image_core.yml
target_name: X410_X4_200
timeout: 720
max_attempts: 2
X410_CG_400:
image_core: x410_400_rfnoc_image_core.yml
target_name: X410_CG_400
timeout: 720
max_attempts: 2
- name: x440_targets_matrix
type: object
displayName: X440 Targets
default:
X440_CG_1600:
image_core: x440_1600_rfnoc_image_core.yml
target_name: X440_CG_1600
timeout: 720
max_attempts: 2
X440_CG_400:
image_core: x440_400_rfnoc_image_core.yml
target_name: X440_CG_400
timeout: 720
max_attempts: 2
X440_X4_1600:
image_core: x440_1600_d_rfnoc_image_core.yml
target_name: X440_X4_1600
timeout: 720
max_attempts: 2
X440_X4_400:
image_core: x440_400_d_rfnoc_image_core.yml
target_name: X440_X4_400
timeout: 720
max_attempts: 2
X440_X4_200:
image_core: x440_200_rfnoc_image_core.yml
target_name: X440_X4_200
timeout: 720
max_attempts: 2
trigger: none
pr:
branches:
include:
- master
paths:
include:
- fpga/usrp3/lib
- fpga/usrp3/top/x400
- fpga/.ci
schedules:
- cron: "0 18 * * Sun"
displayName: Weekly FPGA PR Build master branch
branches:
include:
- master
always: true
extends:
template: templates/stages-fpga-pipeline.yml
parameters:
run_testbenches: ${{ parameters.run_testbenches }}
clean_ip_build: ${{ parameters.clean_ip_build }}
publish_int_files: true
package_and_publish_images: ${{ parameters.package_and_publish_images }}
package_access: ${{ parameters.package_access }}
build_x410: ${{ parameters.build_x410 }}
build_x440: ${{ parameters.build_x440 }}
x410_targets_matrix: ${{ parameters.x410_targets_matrix }}
x440_targets_matrix: ${{ parameters.x440_targets_matrix }}
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