blob: 96e560e0aec491e643175b9153036b874a8e22a5 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
|
#
# Copyright 2022 Ettus Research, a National Instruments Brand
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
# Description:
#
# This template defines a stages-based pipeline that may be leveraged by both
# a PR pipeline or a continuous delivery pipeline.
#
# See https://aka.ms/yaml for pipeline YAML documentation.
#
parameters:
## Optional parameters
# Run testbenches
- name: run_testbenches
type: boolean
default: true
# Option to ignore cached artifacts (if available) and perform
# a clean IP build.
- name: clean_ip_build
type: boolean
default: false
# Number of parallel jobs to use for IP build
- name: num_ip_jobs
type: number
default: 5
# Option to publish intermediate files
- name: publish_int_files
type: boolean
default: false
# Package and publish images
- name: package_and_publish_images
type: boolean
default: true
# Package access in the SDR server ('Internal' or 'Public')
- name: package_access
type: string
default: 'Internal'
# Build X410 FPGA targets
- name: build_x410
type: boolean
default: true
# X410 FPGA targets to build (if build_x410 is true)
- name: x410_targets_matrix
type: object
default:
X410_X4_200:
image_core: x410_200_rfnoc_image_core.yml
target_name: X410_X4_200
timeout: 720
max_attempts: 2
X410_UC_200:
image_core: x410_200_rfnoc_image_core.yml
target_name: X410_UC_200
timeout: 720
max_attempts: 2
X410_X4_400:
image_core: x410_400_d_rfnoc_image_core.yml
target_name: X410_X4_400
timeout: 720
max_attempts: 2
X410_CG_400:
image_core: x410_400_rfnoc_image_core.yml
target_name: X410_CG_400
timeout: 720
max_attempts: 2
# Build X440 FPGA targets
- name: build_x440
type: boolean
default: true
# X440 FPGA targets to build (if build_x440 is true)
- name: x440_targets_matrix
type: object
default:
X440_CG_1600:
image_core: x440_1600_rfnoc_image_core.yml
target_name: X440_CG_1600
timeout: 720
max_attempts: 2
X440_CG_400:
image_core: x440_400_rfnoc_image_core.yml
target_name: X440_CG_400
timeout: 720
max_attempts: 2
X440_X4_1600:
image_core: x440_1600_d_rfnoc_image_core.yml
target_name: X440_X4_1600
timeout: 720
max_attempts: 2
X440_X4_400:
image_core: x440_400_d_rfnoc_image_core.yml
target_name: X440_X4_400
timeout: 720
max_attempts: 2
X440_X4_200:
image_core: x440_200_rfnoc_image_core.yml
target_name: X440_X4_200
timeout: 720
max_attempts: 2
resources:
repositories:
- repository: hwtools
type: git
ref: main
name: DevCentral/hwtools
stages:
### START: Testbenches stage
- stage: run_testbenches_stage
displayName: Run Testbenches
dependsOn: []
condition: and(succeeded(), eq('${{ parameters.run_testbenches }}', 'true'))
jobs:
- template: job-run-testbenches.yml
### END: Testbenches stage
### START: X410 stages
- stage: build_x410_ip_stage
displayName: Build X410 IP
dependsOn: []
condition: and(succeeded(), eq('${{ parameters.build_x410 }}', 'true'))
jobs:
- template: job-build-ip.yml
parameters:
directory: uhddev/fpga/usrp3/top/x400
ip_target: X410_IP
clean_build: ${{ parameters.clean_ip_build }}
num_jobs: ${{ parameters.num_ip_jobs }}
- stage: build_x410_targets_stage
displayName: Build X410 FPGA Targets
dependsOn: build_x410_ip_stage
condition: succeeded('build_x410_ip_stage')
jobs:
- template: job-build-fpga.yml
parameters:
targets_matrix: ${{ parameters.x410_targets_matrix }}
ip_artifact: X410_IP
top_dir: uhddev/fpga/usrp3/top/x400
publish_int_files: ${{ parameters.publish_int_files }}
- stage: create_x410_packages_stage
displayName: Package & Publish X410 Binaries
dependsOn: build_x410_targets_stage
condition: and(succeeded('build_x410_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
jobs:
- template: job-package-images.yml
parameters:
package_name: x4xx_x410_fpga_default
artifacts_matrix: ${{ parameters.x410_targets_matrix }}
build_directory: uhddev/fpga/usrp3/top/x400/build/
package_access: ${{ parameters.package_access }}
### END: X410 stages
### START: X440 stages
- stage: build_x440_ip_stage
displayName: Build X440 IP
dependsOn: []
condition: and(succeeded(), eq('${{ parameters.build_x440 }}', 'true'))
jobs:
- template: job-build-ip.yml
parameters:
directory: uhddev/fpga/usrp3/top/x400
ip_target: X440_IP
clean_build: ${{ parameters.clean_ip_build }}
- stage: build_x440_targets_stage
displayName: Build X440 FPGA Targets
dependsOn: build_x440_ip_stage
condition: succeeded('build_x440_ip_stage')
jobs:
- template: job-build-fpga.yml
parameters:
targets_matrix: ${{ parameters.x440_targets_matrix }}
ip_artifact: X440_IP
top_dir: uhddev/fpga/usrp3/top/x400
publish_int_files: ${{ parameters.publish_int_files }}
- stage: create_x440_packages_stage
displayName: Package & Publish X440 Binaries
dependsOn: build_x440_targets_stage
condition: and(succeeded('build_x440_targets_stage'), eq('${{ parameters.package_and_publish_images }}', 'true'))
jobs:
- template: job-package-images.yml
parameters:
package_name: x4xx_x440_fpga_default
artifacts_matrix: ${{ parameters.x440_targets_matrix }}
build_directory: uhddev/fpga/usrp3/top/x400/build/
package_access: ${{ parameters.package_access }}
### END: X440 stages
|
