blob: 6707df484ba715911b4e66e6a9d028581fe26b92 (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
|
<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="zbx_top_cpld" device="LCMXO3LF-9400C-6BG256I" default_implementation="impl1">
<Options/>
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="zbx_cpld_strat">
<Options VERILOG_DIRECTIVES="VARIANT_XO3" def_top="zbx_top_cpld" top="zbx_top_cpld"/>
<Source name="../zbx_cpld_core.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../zbx_top_cpld.v" type="Verilog" type_short="Verilog">
<Options top_module="zbx_top_cpld"/>
</Source>
<Source name="../../../../../../lib/control/handshake.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/pulse_synchronizer.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/ram_2port.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/reset_sync.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/synchronizer.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/control/synchronizer_impl.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/common/reconfig_engine.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../ctrlport_byte_deserializer.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_splitter.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_clgen.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_shift.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/wb_spi/rtl/verilog/spi_top.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/common/spi_slave.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../cpld/common/spi_slave_to_ctrlport_master.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_window.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/atr_controller.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/basic_regs.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/dsa_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/led_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/lo_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/power_regs.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../register_endpoints/switch_control.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_clk_cross.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="../../../../../../lib/rfnoc/utils/ctrlport_combiner.v" type="Verilog" type_short="Verilog">
<Options/>
</Source>
<Source name="ip/pll/pll.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="zbx_top_cpld.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
<Source name="../zbx_top_cpld_gpio.ldc" type="LSE Design Constraints File" type_short="LDC" excluded="TRUE">
<Options/>
</Source>
</Implementation>
<Strategy name="zbx_cpld_strat" file="zbx_top_cpld.sty"/>
</BaliProject>
|
