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| author |   Leonid Ravich <Leonid.Ravich@emc.com> | 2020-07-01 21:48:12 +0300 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2020-07-06 14:49:34 +0530 |
| commit | 87730ccbddcb48478b1b88e88b14e73424130764 (patch) | |
| tree | a5102830f2c7167f725e684b76e7e64980ea6053 /MAINTAINERS | |
| parent | dmaengine: fsl-edma: fix wrong tcd endianness for big-endian cpu (diff) | |
| download | wireguard-linux-87730ccbddcb48478b1b88e88b14e73424130764.tar.xz wireguard-linux-87730ccbddcb48478b1b88e88b14e73424130764.zip | |
dmaengine: ioat setting ioat timeout as module parameter
DMA transaction time to completion is a function of PCI bandwidth,
transaction size and a queue depth. So hard coded value for timeouts
might be wrong for some scenarios.
Signed-off-by: Leonid Ravich <Leonid.Ravich@emc.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20200701184816.29138-1-leonid.ravich@dell.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions