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| author |   Chris Brandt <chris.brandt@renesas.com> | 2017-01-23 08:55:19 -0500 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-01-24 13:25:30 +0100 |
| commit | 69b5c6dceaa138859f03ca20e3adca7ddec6bae7 (patch) | |
| tree | 05bbd706fc660184f1ae465ad07ac414db9c4360 /arch/arm/boot/dts/r7s72100.dtsi | |
| parent | ARM: dts: r7s72100: add ostm clock to device tree (diff) | |
| download | wireguard-linux-69b5c6dceaa138859f03ca20e3adca7ddec6bae7.tar.xz wireguard-linux-69b5c6dceaa138859f03ca20e3adca7ddec6bae7.zip | |
ARM: dts: r7s72100: add ostm to device tree
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r7s72100.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r7s72100.dtsi | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index d5946df29222..74e684f3c1c7 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -505,4 +505,22 @@ cap-sdio-irq; status = "disabled"; }; + + ostm0: timer@fcfec000 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec000 0x30>; + interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>; + clocks = <&mstp5_clks R7S72100_CLK_OSTM0>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + ostm1: timer@fcfec400 { + compatible = "renesas,r7s72100-ostm", "renesas,ostm"; + reg = <0xfcfec400 0x30>; + interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>; + clocks = <&mstp5_clks R7S72100_CLK_OSTM1>; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; }; |