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| author |   Atish Patra <atishp@rivosinc.com> | 2022-07-22 09:50:46 -0700 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-11 14:36:55 -0700 |
| commit | 9f7a8ff6391fd5363363b8e5c8b1462a07922368 (patch) | |
| tree | 6ea3c4b80dbecb0de1071c630daafe6babc34090 /arch/riscv/include/asm/csr.h | |
| parent | RISC-V: Enable sstc extension parsing from DT (diff) | |
| download | wireguard-linux-9f7a8ff6391fd5363363b8e5c8b1462a07922368.tar.xz wireguard-linux-9f7a8ff6391fd5363363b8e5c8b1462a07922368.zip | |
RISC-V: Prefer sstc extension if available
RISC-V ISA has sstc extension which allows updating the next clock event
via a CSR (stimecmp) instead of an SBI call. This should happen dynamically
if sstc extension is available. Otherwise, it will fallback to SBI call
to maintain backward compatibility.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20220722165047.519994-4-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/asm/csr.h')
0 files changed, 0 insertions, 0 deletions