wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2024-02-29	riscv: Fix enabling cbo.zero when running in M-mode	Samuel Holland	1	-0/+2
2024-01-17	RISC-V: Implement archrandom when Zkr is available	Samuel Ortiz	1	-0/+9
2023-10-12	RISCV: KVM: Add sstateen0 context save/restore	Mayuresh Chitale	1	-0/+1
2023-10-12	RISCV: KVM: Add senvcfg context save/restore	Mayuresh Chitale	1	-0/+1
2023-10-12	RISC-V: KVM: Enable Smstateen accesses	Mayuresh Chitale	1	-0/+16
2023-08-08	RISC-V: KVM: provide UAPI for host SATP mode	Daniel Henrique Barboza	1	-0/+2
2023-07-03	Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm	Linus Torvalds	1	-0/+2
2023-06-08	riscv: Add new csr defines related to vector extension	Greentime Hu	1	-2/+16
2023-06-06	RISC-V: KVM: Redirect AMO load/store misaligned traps to guest	wchen	1	-0/+2
2023-05-05	Merge tag 'kvm-riscv-6.4-1' of https://github.com/kvm-riscv/linux into HEAD	Paolo Bonzini	1	-7/+100
2023-04-21	RISC-V: KVM: Drop the _MASK suffix from hgatp.VMID mask defines	Anup Patel	1	-6/+6
2023-04-21	RISC-V: Add AIA related CSR defines	Anup Patel	1	-1/+94
2023-03-23	riscv: entry: Convert to generic entry	Guo Ren	1	-1/+0
2022-08-11	RISC-V: Add Sstc extension support	Palmer Dabbelt	1	-0/+5
2022-08-11	RISC-V: Add SSTC extension CSR details	Atish Patra	1	-0/+5
2022-07-29	RISC-V: KVM: Add support for Svpbmt inside Guest/VM	Anup Patel	1	-0/+16
2022-05-31	Merge tag 'riscv-for-linus-5.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux	Linus Torvalds	1	-0/+7
2022-05-20	RISC-V: KVM: Add Sv57x4 mode support for G-stage	Anup Patel	1	-0/+1
2022-04-26	riscv: compat: syscall: Add entry.S implementation	Guo Ren	1	-0/+7
2022-03-21	perf: RISC-V: Add support for SBI PMU and Sscofpmf	Palmer Dabbelt	1	-1/+65
2022-03-21	RISC-V: Add sscofpmf extension support	Atish Patra	1	-1/+7
2022-03-21	RISC-V: Add CSR encodings for all HPMCOUNTERS	Atish Patra	1	-0/+58
2022-02-14	riscv: mm: Set sv57 on defaultly	Qinglin Pan	1	-0/+1
2022-01-19	riscv: Implement sv48 support	Alexandre Ghiti	1	-2/+1
2021-10-04	RISC-V: Add hypervisor extension related CSR defines	Anup Patel	1	-0/+87
2021-04-26	riscv: Introduce alternative mechanism to apply errata solution	Vincent Chen	1	-0/+3
2021-02-18	RISC-V: Implement ASID allocator	Anup Patel	1	-0/+6
2020-05-04	RISC-V: Remove N-extension related defines	Anup Patel	1	-3/+0
2020-02-18	riscv: set pmp configuration if kernel is running in M-mode	Greentime Hu	1	-0/+12
2020-01-04	riscv: prefix IRQ_ macro names with an RV_ namespace	Paul Walmsley	1	-9/+9
2019-11-17	riscv: clear the instruction cache and all registers when booting	Christoph Hellwig	1	-0/+1
2019-11-17	riscv: read the hart ID from mhartid on boot	Damien Le Moal	1	-0/+1
2019-11-05	riscv: abstract out CSR names for supervisor vs machine mode	Christoph Hellwig	1	-10/+62
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286	Thomas Gleixner	1	-9/+1
2019-05-16	RISC-V: Access CSRs using CSR numbers	Anup Patel	1	-7/+25
2019-05-16	RISC-V: Add interrupt related SCAUSE defines in asm/csr.h	Anup Patel	1	-4/+17
2019-05-16	RISC-V: Use tabs to align macro values in asm/csr.h	Anup Patel	1	-38/+38
2018-08-13	RISC-V: add a definition for the SIE SEIE bit	Christoph Hellwig	1	-0/+1
2018-01-30	riscv: rename sptbr to satp	Christoph Hellwig	1	-7/+7
2018-01-07	riscv: rename SR_* constants to match the spec	Christoph Hellwig	1	-4/+4
2017-09-26	RISC-V: Generic library routines and assembly	Palmer Dabbelt	1	-0/+132