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| author |   Guo Ren <guoren@linux.alibaba.com> | 2022-04-05 15:13:06 +0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2022-04-26 13:36:31 -0700 |
| commit | dfb0bfa738f5c58b5c6e81262a0ee4ba154c3f28 (patch) | |
| tree | e9110b38f8891d3d31f0ac4c601caadb7a83f520 /arch/riscv/include/asm/csr.h | |
| parent | riscv: compat: syscall: Add compat_sys_call_table implementation (diff) | |
| download | wireguard-linux-dfb0bfa738f5c58b5c6e81262a0ee4ba154c3f28.tar.xz wireguard-linux-dfb0bfa738f5c58b5c6e81262a0ee4ba154c3f28.zip | |
riscv: compat: syscall: Add entry.S implementation
Implement the entry of compat_sys_call_table[] in asm. Ref to
riscv-privileged spec 4.1.1 Supervisor Status Register (sstatus):
BIT[32:33] = UXL[1:0]:
- 1:32
- 2:64
- 3:128
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20220405071314.3225832-13-guoren@kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/asm/csr.h')
| -rw-r--r-- | arch/riscv/include/asm/csr.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index e935f27b10fd..f5d1251fd6c7 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -36,6 +36,13 @@ #define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */ #endif +#ifdef CONFIG_64BIT +#define SR_UXL _AC(0x300000000, UL) /* XLEN mask for U-mode */ +#define SR_UXL_32 _AC(0x100000000, UL) /* XLEN = 32 for U-mode */ +#define SR_UXL_64 _AC(0x200000000, UL) /* XLEN = 64 for U-mode */ +#define SR_UXL_SHIFT 32 +#endif + /* SATP flags */ #ifndef CONFIG_64BIT #define SATP_PPN _AC(0x003FFFFF, UL) |