diff options
| author |   Yazen Ghannam <yazen.ghannam@amd.com> | 2023-06-13 09:11:42 -0500 |
|---|---|---|
| committer |   Borislav Petkov (AMD) <bp@alien8.de> | 2023-10-16 15:37:01 +0200 |
| commit | 1bae0cfe4a171ccc5f731426296e45beafa096b8 (patch) | |
| tree | b719f6f816e53d74397ab76da64b6f24610dbc45 /arch/x86/kernel/cpu/mce/intel.c | |
| parent | x86/mce: Define amd_mce_usable_address() (diff) | |
| download | wireguard-linux-1bae0cfe4a171ccc5f731426296e45beafa096b8.tar.xz wireguard-linux-1bae0cfe4a171ccc5f731426296e45beafa096b8.zip | |
x86/mce: Cleanup mce_usable_address()
Move Intel-specific checks into a helper function.
Explicitly use "bool" for return type.
No functional change intended.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Link: https://lore.kernel.org/r/20230613141142.36801-4-yazen.ghannam@amd.com
Diffstat (limited to 'arch/x86/kernel/cpu/mce/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/mce/intel.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index f5323551c1a9..52bce533ddcc 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -536,3 +536,23 @@ bool intel_filter_mce(struct mce *m) return false; } + +/* + * Check if the address reported by the CPU is in a format we can parse. + * It would be possible to add code for most other cases, but all would + * be somewhat complicated (e.g. segment offset would require an instruction + * parser). So only support physical addresses up to page granularity for now. + */ +bool intel_mce_usable_address(struct mce *m) +{ + if (!(m->status & MCI_STATUS_MISCV)) + return false; + + if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT) + return false; + + if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS) + return false; + + return true; +} |