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path: root/arch/x86/kernel/cpu/mce/intel.c (follow)
AgeCommit message (Expand)AuthorFilesLines
2023-12-15x86/mce: Handle Intel threshold interrupt stormsTony Luck1-50/+155
2023-12-15x86/mce: Remove old CMCI storm mitigation codeTony Luck1-145/+0
2023-10-16x86/mce: Cleanup mce_usable_address()Yazen Ghannam1-0/+20
2023-07-21x86/mce: Prevent duplicate error recordsBorislav Petkov (AMD)1-1/+18
2022-02-01x86/cpu: Merge Intel and AMD ppin_init() functionsTony Luck1-42/+0
2022-01-25x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPINTony Luck1-0/+1
2021-11-12x86/mce: Add errata workaround for Skylake SKX37Dave Jones1-2/+3
2021-03-20x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPINTony Luck1-0/+1
2021-02-08thermal: Move therm_throt there from x86/mceBorislav Petkov1-1/+0
2020-11-16x86/mce: Use "safe" MSR functions when enabling additional error loggingTony Luck1-2/+3
2020-11-02x86/mce: Enable additional error logging on certain Intel CPUsTony Luck1-0/+20
2020-08-23treewide: Use fallthrough pseudo-keywordGustavo A. R. Silva1-1/+1
2020-03-30Merge tag 'ras_updates_for_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tipLinus Torvalds1-0/+17
2020-02-27x86/mce: Fix logic and comments around MSR_PPIN_CTLTony Luck1-4/+5
2020-02-19x86/mce: Do not log spurious corrected mce errorsPrarit Bhargava1-0/+17
2020-01-13x86/mce: WARN once if IA32_FEAT_CTL MSR is left unlockedSean Christopherson1-5/+6
2020-01-13x86/msr-index: Clean up bit defines for IA32_FEATURE_CONTROL MSRSean Christopherson1-5/+5
2019-11-01x86/mce: Add Xeon Icelake to list of CPUs that support PPINTony Luck1-0/+1
2019-10-01x86/mce: Add Zhaoxin LMCE supportTony W Wang-oc1-2/+2
2019-10-01x86/mce: Add Zhaoxin CMCI supportTony W Wang-oc1-2/+4
2019-08-28x86/intel: Aggregate microserver namingPeter Zijlstra1-1/+1
2018-12-05x86/mce: Streamline MCE subsystem's namingBorislav Petkov1-0/+518