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| author |   Sean Christopherson <sean.j.christopherson@intel.com> | 2019-12-20 20:44:59 -0800 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2020-01-13 17:47:18 +0100 |
| commit | 6d527cebfa04ba4792be9e79e0d7cab22ab6c377 (patch) | |
| tree | 58125116880f9e96f829635f041628f27f41ec76 /arch/x86/kernel/cpu/mce/intel.c | |
| parent | x86/intel: Initialize IA32_FEAT_CTL MSR at boot (diff) | |
| download | wireguard-linux-6d527cebfa04ba4792be9e79e0d7cab22ab6c377.tar.xz wireguard-linux-6d527cebfa04ba4792be9e79e0d7cab22ab6c377.zip | |
x86/mce: WARN once if IA32_FEAT_CTL MSR is left unlocked
WARN if the IA32_FEAT_CTL MSR is somehow left unlocked now that CPU
initialization unconditionally locks the MSR.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20191221044513.21680-6-sean.j.christopherson@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/mce/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/mce/intel.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index c238518b84a2..5627b1091b85 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -116,14 +116,15 @@ static bool lmce_supported(void) /* * BIOS should indicate support for LMCE by setting bit 20 in * IA32_FEAT_CTL without which touching MCG_EXT_CTL will generate a #GP - * fault. + * fault. The MSR must also be locked for LMCE_ENABLED to take effect. + * WARN if the MSR isn't locked as init_ia32_feat_ctl() unconditionally + * locks the MSR in the event that it wasn't already locked by BIOS. */ rdmsrl(MSR_IA32_FEAT_CTL, tmp); - if ((tmp & (FEAT_CTL_LOCKED | FEAT_CTL_LMCE_ENABLED)) == - (FEAT_CTL_LOCKED | FEAT_CTL_LMCE_ENABLED)) - return true; + if (WARN_ON_ONCE(!(tmp & FEAT_CTL_LOCKED))) + return false; - return false; + return tmp & FEAT_CTL_LMCE_ENABLED; } bool mce_intel_cmci_poll(void) |