diff options
| author |   Tony Luck <tony.luck@intel.com> | 2022-01-21 09:47:38 -0800 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2022-01-25 18:40:30 +0100 |
| commit | e464121f2d40eabc7d11823fb26db807ce945df4 (patch) | |
| tree | dccb485c4016c29e2ad77e76f2c922167e90b14c /arch/x86/kernel/cpu/mce/intel.c | |
| parent | x86/MCE/AMD: Allow thresholding interface updates after init (diff) | |
| download | wireguard-linux-e464121f2d40eabc7d11823fb26db807ce945df4.tar.xz wireguard-linux-e464121f2d40eabc7d11823fb26db807ce945df4.zip | |
x86/cpu: Add Xeon Icelake-D to list of CPUs that support PPIN
Missed adding the Icelake-D CPU to the list. It uses the same MSRs
to control and read the inventory number as all the other models.
Fixes: dc6b025de95b ("x86/mce: Add Xeon Icelake to list of CPUs that support PPIN")
Reported-by: Ailin Xu <ailin.xu@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/20220121174743.1875294-2-tony.luck@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/mce/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/mce/intel.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index bb9a46a804bf..baafbb37be67 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: case INTEL_FAM6_ICELAKE_X: + case INTEL_FAM6_ICELAKE_D: case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: |