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| author |   Tony Luck <tony.luck@intel.com> | 2019-10-28 09:37:19 -0700 |
|---|---|---|
| committer |   Borislav Petkov <bp@suse.de> | 2019-11-01 17:29:36 +0100 |
| commit | dc6b025de95bcd22ff37c4fabb022ec8a027abf1 (patch) | |
| tree | a386a4d78a55c5bac68cb145d92798bcba3e1487 /arch/x86/kernel/cpu/mce/intel.c | |
| parent | x86/mce: Lower throttling MCE messages' priority to warning (diff) | |
| download | wireguard-linux-dc6b025de95bcd22ff37c4fabb022ec8a027abf1.tar.xz wireguard-linux-dc6b025de95bcd22ff37c4fabb022ec8a027abf1.zip | |
x86/mce: Add Xeon Icelake to list of CPUs that support PPIN
New CPU model, same MSRs to control and read the inventory number.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20191028163719.19708-1-tony.luck@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/mce/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/mce/intel.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index 68a1d25c971e..e270d0770134 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -484,6 +484,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_D: case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: + case INTEL_FAM6_ICELAKE_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: |