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| author |   Tony Luck <tony.luck@intel.com> | 2021-03-19 10:39:19 -0700 |
|---|---|---|
| committer |   Ingo Molnar <mingo@kernel.org> | 2021-03-20 12:12:10 +0100 |
| commit | a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab (patch) | |
| tree | e185837b47cc1d234605420fe76c7ceac8853424 /arch/x86/kernel/cpu/mce/intel.c | |
| parent | objtool/x86: Use asm/nops.h (diff) | |
| download | wireguard-linux-a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab.tar.xz wireguard-linux-a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab.zip | |
x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
New CPU model, same MSRs to control and read the inventory number.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
Diffstat (limited to 'arch/x86/kernel/cpu/mce/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/mce/intel.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index e309476743b7..acfd5d9f93c6 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) case INTEL_FAM6_BROADWELL_X: case INTEL_FAM6_SKYLAKE_X: case INTEL_FAM6_ICELAKE_X: + case INTEL_FAM6_SAPPHIRERAPIDS_X: case INTEL_FAM6_XEON_PHI_KNL: case INTEL_FAM6_XEON_PHI_KNM: |