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authorClaudiu Beznea <claudiu.beznea@microchip.com>2020-07-22 10:38:19 +0300
committerStephen Boyd <sboyd@kernel.org>2020-07-24 02:19:08 -0700
commit22a1dfe93bf496d03cb1d76b1fbd23a7ff4a062c (patch)
treefe31d07e2593dcc5f7c90af7bc263cfbfa1e7861 /drivers/clk/at91/dt-compat.c
parentclk: at91: clk-generated: pass the id of changeable parent at registration (diff)
downloadwireguard-linux-22a1dfe93bf496d03cb1d76b1fbd23a7ff4a062c.tar.xz
wireguard-linux-22a1dfe93bf496d03cb1d76b1fbd23a7ff4a062c.zip
clk: at91: clk-generated: add mux_table option
Add mux table option. This is necessary for IP versions that has gaps in the range of available clock sources (e.g. SAMA7G5). Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1595403506-8209-12-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91/dt-compat.c')
-rw-r--r--drivers/clk/at91/dt-compat.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c
index 8a652c44c25a..cc95d42f4d53 100644
--- a/drivers/clk/at91/dt-compat.c
+++ b/drivers/clk/at91/dt-compat.c
@@ -158,8 +158,9 @@ static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
&dt_pcr_layout, name,
- parent_names, num_parents,
- id, &range, chg_pid);
+ parent_names, NULL,
+ num_parents, id, &range,
+ chg_pid);
if (IS_ERR(hw))
continue;