diff options
| author |   Stephen Boyd <sboyd@codeaurora.org> | 2015-06-29 16:56:30 -0700 |
|---|---|---|
| committer |   Michael Turquette <mturquette@baylibre.com> | 2015-08-24 16:48:44 -0700 |
| commit | 98d8a60eccee74165793379f1f8a3b1cef3131c7 (patch) | |
| tree | 43acc8e09d585a34910faa070b972c48d03a4f55 /drivers/clk/clk-si5351.c | |
| parent | clk: Replace __clk_get_num_parents with clk_hw_get_num_parents() (diff) | |
| download | wireguard-linux-98d8a60eccee74165793379f1f8a3b1cef3131c7.tar.xz wireguard-linux-98d8a60eccee74165793379f1f8a3b1cef3131c7.zip | |
clk: Convert __clk_get_flags() to clk_hw_get_flags()
Mostly converted with the following snippet:
@@
struct clk_hw *E;
@@
-__clk_get_flags(E->clk)
+clk_hw_get_flags(E)
Acked-by: Tero Kristo <t-kristo@ti.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Daniel Thompson <daniel.thompson@linaro.org>
Cc: Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-si5351.c')
| -rw-r--r-- | drivers/clk/clk-si5351.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 9e6de57eae3b..4b2ee39f05fd 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -663,7 +663,7 @@ static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate, divby4 = 1; /* multisync can set pll */ - if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { /* * find largest integer divider for max * vco frequency and given target rate @@ -1013,7 +1013,7 @@ static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate, rate = SI5351_CLKOUT_MIN_FREQ; /* request frequency if multisync master */ - if (__clk_get_flags(hwdata->hw.clk) & CLK_SET_RATE_PARENT) { + if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { /* use r divider for frequencies below 1MHz */ rdiv = SI5351_OUTPUT_CLK_DIV_1; while (rate < SI5351_MULTISYNTH_MIN_FREQ && |