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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2023-11-22 14:23:06 +0000 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2023-12-17 15:56:14 -0800 |
| commit | eb16ddb838dd8602961b5fc17d1350cd41ae69e0 (patch) | |
| tree | 421711d7787f314e1769dc3d4cee3e3fd843606f /drivers/clk/clk-versaclock3.c | |
| parent | Linux 6.7-rc1 (diff) | |
| download | wireguard-linux-eb16ddb838dd8602961b5fc17d1350cd41ae69e0.tar.xz wireguard-linux-eb16ddb838dd8602961b5fc17d1350cd41ae69e0.zip | |
clk: versaclock3: Update vc3_get_div() to avoid divide by zero
Update vc3_get_div() to avoid divide by zero operation on
vc3_div_round_rate() by returning1, if there is no table match
found.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20231122142310.203169-2-biju.das.jz@bp.renesas.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-versaclock3.c')
| -rw-r--r-- | drivers/clk/clk-versaclock3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk-versaclock3.c b/drivers/clk/clk-versaclock3.c index 00930d7bca77..3aad69a08512 100644 --- a/drivers/clk/clk-versaclock3.c +++ b/drivers/clk/clk-versaclock3.c @@ -477,7 +477,7 @@ static unsigned int vc3_get_div(const struct clk_div_table *table, if (clkt->val == val) return clkt->div; - return 0; + return 1; } static unsigned long vc3_div_recalc_rate(struct clk_hw *hw, |