diff options
| author |   Paul Cercueil <paul@crapouillou.net> | 2021-05-30 17:49:21 +0100 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2021-06-27 19:49:17 -0700 |
| commit | 037f1ffd0f0a6bad89e17aa4698c97ef430c6ad1 (patch) | |
| tree | a9bfcfae8cfa961c5caba6119ec444bd857be429 /drivers/clk/ingenic | |
| parent | clk: ingenic: Read bypass register only when there is one (diff) | |
| download | wireguard-linux-037f1ffd0f0a6bad89e17aa4698c97ef430c6ad1.tar.xz wireguard-linux-037f1ffd0f0a6bad89e17aa4698c97ef430c6ad1.zip | |
clk: ingenic: Remove pll_info.no_bypass_bit
We can express that a PLL has no bypass bit by simply setting the
.bypass_bit field to a negative value.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20210530164923.18134-5-paul@crapouillou.net
Tested-by: 周琰杰 (Zhou Yanjie)<zhouyanjie@wanyeetech.com> # on CU1830-neo/X1830
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/ingenic')
| -rw-r--r-- | drivers/clk/ingenic/cgu.c | 4 | ||||
| -rw-r--r-- | drivers/clk/ingenic/cgu.h | 7 | ||||
| -rw-r--r-- | drivers/clk/ingenic/jz4770-cgu.c | 3 |
3 files changed, 6 insertions, 8 deletions
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c index 7686072aff8f..58f7ab5cf0fe 100644 --- a/drivers/clk/ingenic/cgu.c +++ b/drivers/clk/ingenic/cgu.c @@ -99,7 +99,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) od_enc = ctl >> pll_info->od_shift; od_enc &= GENMASK(pll_info->od_bits - 1, 0); - if (!pll_info->no_bypass_bit) { + if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); bypass = !!(ctl & BIT(pll_info->bypass_bit)); @@ -226,7 +226,7 @@ static int ingenic_pll_enable(struct clk_hw *hw) u32 ctl; spin_lock_irqsave(&cgu->lock, flags); - if (!pll_info->no_bypass_bit) { + if (pll_info->bypass_bit >= 0) { ctl = readl(cgu->base + pll_info->bypass_reg); ctl &= ~BIT(pll_info->bypass_bit); diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h index 44d97a259692..10521d1b7b12 100644 --- a/drivers/clk/ingenic/cgu.h +++ b/drivers/clk/ingenic/cgu.h @@ -39,10 +39,10 @@ * their encoded values in the PLL control register, or -1 for * unsupported values * @bypass_reg: the offset of the bypass control register within the CGU - * @bypass_bit: the index of the bypass bit in the PLL control register + * @bypass_bit: the index of the bypass bit in the PLL control register, or + * -1 if there is no bypass bit * @enable_bit: the index of the enable bit in the PLL control register * @stable_bit: the index of the stable bit in the PLL control register - * @no_bypass_bit: if set, the PLL has no bypass functionality */ struct ingenic_cgu_pll_info { unsigned reg; @@ -52,10 +52,9 @@ struct ingenic_cgu_pll_info { u8 n_shift, n_bits, n_offset; u8 od_shift, od_bits, od_max; unsigned bypass_reg; - u8 bypass_bit; + s8 bypass_bit; u8 enable_bit; u8 stable_bit; - bool no_bypass_bit; }; /** diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c index 381a27f20b51..2321742b3471 100644 --- a/drivers/clk/ingenic/jz4770-cgu.c +++ b/drivers/clk/ingenic/jz4770-cgu.c @@ -139,8 +139,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = { .od_bits = 2, .od_max = 8, .od_encoding = pll_od_encoding, - .bypass_reg = CGU_REG_CPPCR1, - .no_bypass_bit = true, + .bypass_bit = -1, .enable_bit = 7, .stable_bit = 6, }, |