diff options
| author |   Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2020-12-26 13:15:54 +0100 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2021-01-04 11:42:25 +0100 |
| commit | 2f290b7c67adf6459a17a4c978102af35cd62e4a (patch) | |
| tree | 229e9083a49bfb60f1012eecdea46120feb62d12 /drivers/clk/meson/clk-pll.c | |
| parent | Linux 5.11-rc1 (diff) | |
| download | wireguard-linux-2f290b7c67adf6459a17a4c978102af35cd62e4a.tar.xz wireguard-linux-2f290b7c67adf6459a17a4c978102af35cd62e4a.zip | |
clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL
The "rate" parameter in meson_clk_pll_set_rate() contains the new rate.
Retrieve the old rate with clk_hw_get_rate() so we don't inifinitely try
to switch from the new rate to the same rate again.
Fixes: 7a29a869434e8b ("clk: meson: Add support for Meson clock controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20201226121556.975418-2-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/clk/meson/clk-pll.c')
| -rw-r--r-- | drivers/clk/meson/clk-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index b17a13e9337c..9404609b5ebf 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -371,7 +371,7 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, if (parent_rate == 0 || rate == 0) return -EINVAL; - old_rate = rate; + old_rate = clk_hw_get_rate(hw); ret = meson_clk_get_pll_settings(rate, parent_rate, &m, &n, pll); if (ret) |