wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-07-11	clk: meson: change usleep_range() to udelay() for atomic context	Dmitry Rokosov	1	-2/+2
2023-06-15	clk: meson: pll: remove unneeded semicolon	Jiapeng Chong	1	-1/+1
2023-05-30	clk: meson: introduce new pll power-on sequence for A1 SoC family	Dmitry Rokosov	1	-0/+23
2023-05-30	clk: meson: make pll rst bit as optional	Dmitry Rokosov	1	-7/+17
2022-12-12	Merge branches 'clk-bindings', 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-ti' into clk-next	Stephen Boyd	1	-8/+12
2022-11-22	clk: Remove a useless include	Christophe JAILLET	1	-1/+0
2022-11-08	clk: meson: pll: add pcie lock retry workaround	Heiner Kallweit	1	-4/+8
2022-11-08	clk: meson: pll: adjust timeout in meson_clk_pll_wait_lock()	Heiner Kallweit	1	-4/+4
2021-05-19	clk: meson: pll: switch to determine_rate for the PLL ops	Martin Blumenstingl	1	-11/+15
2021-01-04	clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()	Martin Blumenstingl	1	-2/+3
2021-01-04	clk: meson: clk-pll: make "ret" a signed integer	Martin Blumenstingl	1	-1/+2
2021-01-04	clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLL	Martin Blumenstingl	1	-1/+1
2020-01-31	Merge branches 'clk-debugfs-danger', 'clk-basic-hw', 'clk-renesas', 'clk-amlogic' and 'clk-allwinner' into clk-next	Stephen Boyd	1	-0/+9
2019-12-23	clk: let init callback return an error code	Jerome Brunet	1	-1/+3
2019-12-16	clk: meson: pll: Fix by 0 division in __pll_params_to_rate()	Remi Pommarel	1	-0/+9
2019-05-07	Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and 'clk-basic-be' into clk-next	Stephen Boyd	1	-0/+26
2019-04-01	clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL	Neil Armstrong	1	-0/+26
2019-03-25	clk: meson: pll: fix rounding and setting a rate that matches precisely	Martin Blumenstingl	1	-1/+1
2019-02-04	clk: meson: pll: update driver for the g12a	Jerome Brunet	1	-57/+146
2019-02-02	clk: meson: rework and clean drivers dependencies	Jerome Brunet	1	-4/+9
2018-11-23	clk: meson: clk-pll: check if the clock is already enabled	Martin Blumenstingl	1	-0/+19
2018-09-26	clk: meson: clk-pll: drop hard-coded rates from pll tables	Jerome Brunet	1	-23/+46
2018-09-26	clk: meson: clk-pll: remove od parameters	Jerome Brunet	1	-27/+13
2018-09-26	clk: meson: clk-pll: add enable bit	Jerome Brunet	1	-5/+42
2018-05-18	clk: meson: use SPDX license identifiers consistently	Jerome Brunet	1	-12/+1
2018-03-13	clk: meson: add ROUND_CLOSEST to the pll driver	Jerome Brunet	1	-4/+13
2018-03-13	clk: meson: improve pll driver results with frac	Jerome Brunet	1	-47/+90
2018-03-13	clk: meson: remove special gp0 lock loop	Jerome Brunet	1	-11/+1
2018-03-13	clk: meson: migrate plls clocks to clk_regmap	Jerome Brunet	1	-150/+93
2018-02-12	clk: meson: fix rate calculation of plls with a fractional part	Jerome Brunet	1	-1/+0
2018-02-12	clk: meson: add od3 to the pll driver	Jerome Brunet	1	-3/+16
2018-02-12	clk: meson: use the frac parameter width instead of a constant	Jerome Brunet	1	-1/+1
2018-02-12	clk: meson: remove unnecessary rounding in the pll clock	Jerome Brunet	1	-8/+9
2018-02-12	clk: meson: check pll rate param table before using it	Jerome Brunet	1	-0/+10
2017-04-04	clk: meson: Add support for parameters for specific PLLs	Neil Armstrong	1	-2/+51
2016-06-22	clk: meson: fractional pll support	Michael Turquette	1	-2/+30
2016-06-22	clk: meson8b: clean up pll clocks	Michael Turquette	1	-61/+11
2015-06-05	clk: meson: Add support for Meson clock controller	Carlo Caione	1	-0/+227