diff options
| author |   Neil Armstrong <narmstrong@baylibre.com> | 2018-11-21 12:19:22 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-11-27 16:30:54 +0100 |
| commit | 21310c39ec01e82ef3ef9bf8ac385b53ccdc158c (patch) | |
| tree | 7e82c1ff4a5a3777eef87294635d348640f501d8 /drivers/clk/meson/gxbb.c | |
| parent | clk: meson: meson8b: add the CPU clock post divider clocks (diff) | |
| download | wireguard-linux-21310c39ec01e82ef3ef9bf8ac385b53ccdc158c.tar.xz wireguard-linux-21310c39ec01e82ef3ef9bf8ac385b53ccdc158c.zip | |
clk: meson: Fix GXL HDMI PLL fractional bits width
The GXL Documentation specifies 12 bits for the Fractional bit field,
bit the last bits have a different purpose that we cannot handle right
now, so update the bitwidth to have correct fractional calculations.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added comment on GXL HHI_HDMI_PLL_CNTL register shift]
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lkml.kernel.org/r/20181121111922.1277-1-narmstrong@baylibre.com
Diffstat (limited to 'drivers/clk/meson/gxbb.c')
| -rw-r--r-- | drivers/clk/meson/gxbb.c | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 30fbf8f1f190..794f6492a93d 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -216,10 +216,16 @@ static struct clk_regmap gxl_hdmi_pll_dco = { .shift = 9, .width = 5, }, + /* + * On gxl, there is a register shift due to + * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb, + * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB + * instead which is defined at the same offset. + */ .frac = { .reg_off = HHI_HDMI_PLL_CNTL2, .shift = 0, - .width = 12, + .width = 10, }, .l = { .reg_off = HHI_HDMI_PLL_CNTL, |