wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-08-30	Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next	Stephen Boyd	1	-424/+424
2023-08-08	clk: meson: eeclk: move bindings include to main driver	Neil Armstrong	1	-0/+2
2023-08-08	clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKS	Neil Armstrong	1	-424/+422
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring	1	-1/+1
2021-11-30	clk: meson: gxbb: Fix the SDM_EN bit for MPLL0 on GXBB	Martin Blumenstingl	1	-3/+41
2020-11-23	clk: meson: enable building as modules	Kevin Hilman	1	-1/+4
2020-04-16	clk: meson: gxbb: Prepare the GPU clock tree to change at runtime	Martin Blumenstingl	1	-18/+22
2020-02-13	clk: meson: gxbb: set audio output clock hierarchy	Jerome Brunet	1	-8/+10
2020-02-13	clk: meson: gxbb: add the gxl internal dac gate	Jerome Brunet	1	-0/+3
2019-10-01	clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate	Martin Blumenstingl	1	-0/+1
2019-07-29	clk: meson: clk-regmap: migrate to new parent description method	Alexandre Mergnat	1	-0/+3
2019-07-29	clk: meson: gxbb: migrate to the new parent description method	Alexandre Mergnat	1	-203/+451
2019-05-20	clk: meson: gxbb: no spread spectrum on mpll0	Jerome Brunet	1	-5/+0
2019-03-19	clk: meson-gxbb: round the vdec dividers to closest	Maxime Jourdan	1	-0/+2
2019-02-04	clk: meson: factorise meson64 peripheral clock controller drivers	Jerome Brunet	1	-75/+197
2019-02-02	clk: meson: rework and clean drivers dependencies	Jerome Brunet	1	-1/+4
2019-01-18	clk: meson: gxbb: claim clock controller input clock from DT	Jerome Brunet	1	-13/+24
2018-12-14	Merge branch 'clk-fixes' into clk-next	Stephen Boyd	1	-0/+12
2018-12-13	Merge tag 'meson-clk-4.21-2' of https://github.com/BayLibre/clk-meson into clk-meson	Stephen Boyd	1	-1/+7
2018-12-03	clk: meson: Mark some things static	Stephen Boyd	1	-4/+4
2018-11-27	clk: meson: Fix GXL HDMI PLL fractional bits width	Neil Armstrong	1	-1/+7
2018-11-23	clk: meson-gxbb: Add video clocks	Neil Armstrong	1	-0/+722
2018-11-23	clk: meson-gxbb: Fix HDMI PLL for GXL SoCs	Neil Armstrong	1	-2/+49
2018-11-08	clk: meson-gxbb: set fclk_div3 as CLK_IS_CRITICAL	Christian Hewitt	1	-0/+12
2018-09-26	clk: meson: clk-pll: drop hard-coded rates from pll tables	Jerome Brunet	1	-60/+60
2018-09-26	clk: meson: clk-pll: remove od parameters	Jerome Brunet	1	-256/+228
2018-09-26	clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary	Jerome Brunet	1	-4/+8
2018-09-26	clk: meson: clk-pll: add enable bit	Jerome Brunet	1	-2/+30
2018-07-09	clk: meson: add gen_clk	Jerome Brunet	1	-0/+66
2018-07-09	clk: meson: stop rate propagation for audio clocks	Jerome Brunet	1	-9/+7
2018-07-09	clk: meson: remove obsolete register access	Jerome Brunet	1	-34/+2
2018-06-19	clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL	Neil Armstrong	1	-0/+1
2018-05-18	clk: meson: use SPDX license identifiers consistently	Jerome Brunet	1	-14/+1
2018-05-15	clk: meson: gxbb: add the video decoder clocks	Maxime Jourdan	1	-0/+114
2018-03-14	clk: meson: Drop unused local variable and add static	Stephen Boyd	1	-2/+2
2018-03-13	clk: meson: clean-up clk81 clocks	Jerome Brunet	1	-4/+2
2018-03-13	clk: meson: add fdiv clock gates	Jerome Brunet	1	-10/+90
2018-03-13	clk: meson: add mpll pre-divider	Jerome Brunet	1	-3/+20
2018-03-13	clk: meson: add gp0 frac parameter for axg and gxl	Jerome Brunet	1	-1/+6
2018-03-13	clk: meson: remove special gp0 lock loop	Jerome Brunet	1	-1/+0
2018-03-13	clk: meson: poke pll CNTL last	Jerome Brunet	1	-2/+2
2018-03-13	clk: meson: use hhi syscon if available	Jerome Brunet	1	-11/+28
2018-03-13	clk: meson: split divider and gate part of mpll	Jerome Brunet	1	-21/+57
2018-03-13	clk: meson: migrate plls clocks to clk_regmap	Jerome Brunet	1	-185/+239
2018-03-13	clk: meson: migrate the audio divider clock to clk_regmap	Jerome Brunet	1	-21/+9
2018-03-13	clk: meson: migrate mplls clocks to clk_regmap	Jerome Brunet	1	-84/+77
2018-03-13	clk: meson: migrate muxes to clk_regmap	Jerome Brunet	1	-160/+150
2018-03-13	clk: meson: migrate dividers to clk_regmap	Jerome Brunet	1	-109/+108
2018-03-13	clk: meson: migrate gates to clk_regmap	Jerome Brunet	1	-129/+137
2018-03-13	clk: meson: add regmap to the clock controllers	Jerome Brunet	1	-10/+23