diff options
| author |   Lubomir Rintel <lkundrak@v3.sk> | 2019-12-18 20:04:54 +0100 |
|---|---|---|
| committer |   Olof Johansson <olof@lixom.net> | 2020-01-06 09:19:07 -0800 |
| commit | 8bea5ac0fbc5b2103f8779ddff216122e3c2e1ad (patch) | |
| tree | fa4a74132c0336e62607cc432695b86f06765e78 /drivers/clk/mmp | |
| parent | ARM: mmp: do not divide the clock rate (diff) | |
| download | wireguard-linux-8bea5ac0fbc5b2103f8779ddff216122e3c2e1ad.tar.xz wireguard-linux-8bea5ac0fbc5b2103f8779ddff216122e3c2e1ad.zip | |
clk: mmp2: Fix the order of timer mux parents
Determined empirically, no documentation is available.
The OLPC XO-1.75 laptop used parent 1, that one being VCTCXO/4 (65MHz), but
thought it's a VCTCXO/2 (130MHz). The mmp2 timer driver, not knowing
what is going on, ended up just dividing the rate as of
commit f36797ee4380 ("ARM: mmp/mmp2: dt: enable the clock")'
Link: https://lore.kernel.org/r/20191218190454.420358-3-lkundrak@v3.sk
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/clk/mmp')
| -rw-r--r-- | drivers/clk/mmp/clk-of-mmp2.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c index a60a1be937ad..b4a95cbbda98 100644 --- a/drivers/clk/mmp/clk-of-mmp2.c +++ b/drivers/clk/mmp/clk-of-mmp2.c @@ -134,7 +134,7 @@ static DEFINE_SPINLOCK(ssp3_lock); static const char *ssp_parent_names[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"}; static DEFINE_SPINLOCK(timer_lock); -static const char *timer_parent_names[] = {"clk32", "vctcxo_2", "vctcxo_4", "vctcxo"}; +static const char *timer_parent_names[] = {"clk32", "vctcxo_4", "vctcxo_2", "vctcxo"}; static DEFINE_SPINLOCK(reset_lock); |