diff options
| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-25 16:34:35 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-31 11:19:21 +0100 |
| commit | ad3393fefd6427999de8d93accb8ea31e1339fa0 (patch) | |
| tree | e1b5f5025e5c737d571af35b5a16d073baf156c3 /drivers/clk/renesas | |
| parent | Merge tag 'renesas-r8a779h0-dt-binding-defs-tag' into renesas-clk-for-v6.9 (diff) | |
| download | wireguard-linux-ad3393fefd6427999de8d93accb8ea31e1339fa0.tar.xz wireguard-linux-ad3393fefd6427999de8d93accb8ea31e1339fa0.zip | |
clk: renesas: rcar-gen4: Add support for FRQCRC1
R-Car V4H and V4M have a second Frequency Control Register C.
Add support for this by treating bit field offsets beyond 31 as
referring to the second register.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f64d5573a92a18505619ff0ff808d50cfc2bde55.1706194617.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen4-cpg.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.c b/drivers/clk/renesas/rcar-gen4-cpg.c index c68d8b987054..a2bbdad021ed 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.c +++ b/drivers/clk/renesas/rcar-gen4-cpg.c @@ -179,7 +179,8 @@ static struct clk * __init cpg_pll_clk_register(const char *name, */ #define CPG_FRQCRB 0x00000804 #define CPG_FRQCRB_KICK BIT(31) -#define CPG_FRQCRC 0x00000808 +#define CPG_FRQCRC0 0x00000808 +#define CPG_FRQCRC1 0x000008e0 struct cpg_z_clk { struct clk_hw hw; @@ -304,7 +305,12 @@ static struct clk * __init cpg_z_clk_register(const char *name, init.parent_names = &parent_name; init.num_parents = 1; - zclk->reg = reg + CPG_FRQCRC; + if (offset < 32) { + zclk->reg = reg + CPG_FRQCRC0; + } else { + zclk->reg = reg + CPG_FRQCRC1; + offset -= 32; + } zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; zclk->mask = GENMASK(offset + 4, offset); |