wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2024-02-20	clk: renesas: r8a779h0: Add RPC-IF clock	Cong Dang	1	-0/+1
2024-02-20	clk: renesas: r8a779h0: Add SYS-DMAC clocks	Cong Dang	1	-0/+2
2024-02-20	clk: renesas: r8a779h0: Add SDHI clock	Cong Dang	1	-0/+1
2024-02-20	clk: renesas: r8a779h0: Add EtherAVB clocks	Cong Dang	1	-0/+3
2024-02-13	clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable	Claudiu Beznea	2	-6/+6
2024-02-13	clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux	Claudiu Beznea	2	-2/+2
2024-02-13	clk: renesas: r8a779f0: Correct PFC/GPIO parent clock	Geert Uytterhoeven	1	-1/+1
2024-02-13	clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks	Geert Uytterhoeven	1	-5/+6
2024-02-06	clk: renesas: r8a779h0: Add I2C clocks	Cong Dang	1	-0/+4
2024-02-06	clk: renesas: r8a779h0: Add watchdog clock	Cong Dang	1	-0/+1
2024-02-06	clk: renesas: r8a779h0: Add PFC/GPIO clocks	Cong Dang	1	-0/+3
2024-01-31	clk: renesas: r8a779g0: Fix PCIe clock name	Geert Uytterhoeven	1	-1/+1
2024-01-31	clk: renesas: cpg-mssr: Add support for R-Car V4M	Cong Dang	5	-0/+254
2024-01-31	clk: renesas: rcar-gen4: Add support for FRQCRC1	Geert Uytterhoeven	1	-2/+8
2024-01-31	clk: renesas: r9a07g043: Add clock and reset entries for CRU	Biju Das	1	-0/+31
2024-01-31	clk: renesas: r9a08g045: Add clock and reset support for watchdog	Claudiu Beznea	1	-0/+3
2024-01-23	clk: renesas: mstp: Remove obsolete clkdev registration	Geert Uytterhoeven	1	-13/+3
2024-01-23	clk: renesas: cpg-mssr: Ignore all clocks assigned to non-Linux system	Kuninori Morimoto	1	-7/+104
2023-12-13	clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1	Claudiu Beznea	1	-0/+10
2023-12-13	clk: renesas: rzg2l: Check reset monitor registers	Claudiu Beznea	1	-15/+44
2023-12-13	clk: renesas: r9a08g045: Add IA55 pclk and its reset	Claudiu Beznea	1	-0/+3
2023-11-27	clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()	Claudiu Beznea	1	-23/+15
2023-11-20	clk: renesas: r8a779g0: Add PCIe clocks	Yoshihiro Shimoda	1	-0/+2
2023-11-20	clk: renesas: r8a779g0: Add EtherTSN clock	Niklas Söderlund	1	-0/+1
2023-10-12	clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2	Claudiu Beznea	1	-0/+34
2023-10-12	clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()	Claudiu Beznea	1	-1/+1
2023-10-10	clk: renesas: Add minimal boot support for RZ/G3S SoC	Claudiu Beznea	5	-1/+228
2023-10-10	clk: renesas: rzg2l: Add divider clock for RZ/G3S	Claudiu Beznea	2	-0/+197
2023-10-10	clk: renesas: rzg2l: Refactor SD mux driver	Claudiu Beznea	4	-51/+139
2023-10-05	clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header	Claudiu Beznea	3	-4/+14
2023-10-05	clk: renesas: rzg2l: Add struct clk_hw_data	Claudiu Beznea	1	-18/+34
2023-10-05	clk: renesas: rzg2l: Add support for RZ/G3S PLL	Claudiu Beznea	2	-4/+48
2023-10-05	clk: renesas: rzg2l: Remove critical area	Claudiu Beznea	1	-4/+1
2023-10-05	clk: renesas: rzg2l: Fix computation formula	Claudiu Beznea	1	-6/+6
2023-10-05	clk: renesas: rzg2l: Trust value returned by hardware	Claudiu Beznea	1	-7/+1
2023-10-05	clk: renesas: rzg2l: Lock around writes to mux register	Claudiu Beznea	2	-11/+14
2023-10-05	clk: renesas: rzg2l: Wait for status bit of SD mux before continuing	Claudiu Beznea	1	-7/+10
2023-10-05	clk: renesas: rcar-gen3: Extend SDnH divider table	Dirk Behme	1	-1/+14
2023-09-26	clk: renesas: r8a7795: Constify r8a7795_*_clks	Marek Vasut	1	-2/+2
2023-09-18	clk: renesas: r9a06g032: Name anonymous structs	Ralph Siemsen	1	-30/+33
2023-09-18	clk: renesas: r9a06g032: Fix kerneldoc warning	Ralph Siemsen	1	-0/+1
2023-09-18	clk: renesas: rzg2l: Use u32 for flag and mux_flags	Claudiu Beznea	1	-2/+2
2023-09-18	clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields	Claudiu Beznea	1	-5/+5
2023-09-18	clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()	Claudiu Beznea	1	-3/+2
2023-09-18	clk: renesas: rzg2l: Use core->name for clock name	Claudiu Beznea	1	-1/+1
2023-09-11	clk: renesas: r9a06g032: Use for_each_compatible_node()	Yang Yingliang	1	-3/+2
2023-08-30	Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'clk-cleanup' into clk-next	Stephen Boyd	17	-19/+73
2023-08-15	clk: renesas: rcar-gen3: Add ADG clocks	Kuninori Morimoto	9	-1/+9
2023-07-27	clk: renesas: r8a77965: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2
2023-07-27	clk: renesas: r8a7796: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2