wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2026-03-26	clk: renesas: Add support for RZ/G3L SoC	Biju Das	5	-1/+167
2026-03-26	clk: renesas: rzg2l: Re-enable critical module clocks during resume	Biju Das	1	-3/+18
2026-03-26	clk: renesas: rzg2l: Add rzg2l_mod_clock_init_mstop_helper()	Biju Das	1	-9/+15
2026-03-26	clk: renesas: rzg2l: Add helper for mod clock enable/disable	Biju Das	1	-3/+11
2026-03-26	clk: renesas: r9a0{7g04[34],8g045}: Add critical reset entries	Biju Das	3	-0/+31
2026-03-26	clk: renesas: rzg2l: Add support for critical resets	Biju Das	2	-0/+37
2026-03-25	clk: renesas: r9a09g056: Remove entries for WDT{0,2,3}	Fabrizio Castro	1	-15/+0
2026-03-25	clk: renesas: r9a06g032: Enable watchdog reset sources	Herve Codina (Schneider Electric)	1	-2/+3
2026-03-25	clk: renesas: cpg-mssr: Use struct_size() helper	Rosen Penev	1	-2/+2
2026-03-20	clk: renesas: r9a09g047: Add PCIe clocks and reset	John Madieu	1	-0/+5
2026-03-20	clk: renesas: r9a09g057: Add PCIe clocks and reset	Lad Prabhakar	1	-0/+5
2026-03-20	clk: renesas: r9a09g056: Add PCIe clocks and reset	Lad Prabhakar	1	-0/+5
2026-03-20	clk: renesas: r9a09g047: Add entries for the RSPIs	Tommaso Merciai	1	-0/+24
2026-03-06	clk: renesas: r9a09g056: Add clock and reset entries for RTC	Ovidiu Panait	1	-0/+4
2026-03-06	clk: renesas: r9a09g057: Remove entries for WDT{0,2,3}	Fabrizio Castro	1	-15/+0
2026-02-24	clk: renesas: r9a09g056: Fix ordering of module clocks array	Ovidiu Panait	1	-18/+18
2026-02-24	clk: renesas: r9a09g057: Fix ordering of module clocks array	Ovidiu Panait	1	-20/+20
2026-02-21	Convert 'alloc_flex' family to use the new default GFP_KERNEL argument	Linus Torvalds	3	-3/+3
2026-02-21	Convert 'alloc_obj' family to use the new default GFP_KERNEL argument	Linus Torvalds	13	-32/+32
2026-02-21	treewide: Replace kmalloc with kmalloc_obj for non-scalar types	Kees Cook	14	-35/+35
2026-01-16	clk: renesas: Add missing log message terminators	Geert Uytterhoeven	4	-9/+9
2026-01-16	clk: renesas: rzg2l: Remove DSI clock rate restrictions	Chris Brandt	1	-31/+143
2026-01-09	clk: renesas: rzv2h: Deassert reset on assert timeout	Biju Das	1	-4/+5
2026-01-09	clk: renesas: rzg2l: Deassert reset on assert timeout	Biju Das	1	-4/+5
2026-01-09	clk: renesas: cpg-mssr: Unlock before reset verification	Lad Prabhakar	1	-3/+3
2026-01-09	clk: renesas: r9a09g056: Add entries for CANFD	Lad Prabhakar	1	-0/+10
2026-01-09	clk: renesas: r9a09g057: Add entries for CANFD	Lad Prabhakar	1	-0/+10
2026-01-09	clk: renesas: r9a09g077: Add CANFD clocks	Lad Prabhakar	1	-1/+12
2026-01-09	clk: renesas: cpg-mssr: Handle RZ/T2H register layout in PM callbacks	Cosmin Tanislav	1	-5/+21
2026-01-08	clk: renesas: cpg-mssr: Simplify pointer math in cpg_rzt2h_mstp_read()	Cosmin Tanislav	1	-14/+6
2025-12-29	clk: renesas: r9a09g056: Add clock and reset entries for TSU	Ovidiu Panait	1	-0/+6
2025-12-23	clk: renesas: r9a09g057: Add entries for RSCIs	Lad Prabhakar	1	-0/+126
2025-12-23	clk: renesas: r9a09g056: Add entries for RSCIs	Lad Prabhakar	1	-0/+126
2025-12-15	clk: renesas: r9a09g056: Add entries for the RSPIs	Lad Prabhakar	1	-0/+24
2025-12-15	clk: renesas: r9a09g056: Add entries for ICU	Lad Prabhakar	1	-0/+3
2025-12-15	clk: renesas: r9a09g056: Add entries for the DMACs	Lad Prabhakar	1	-0/+19
2025-12-15	clk: renesas: r9a09g077: Propagate rate changes through mux parents	Lad Prabhakar	1	-1/+1
2025-12-15	clk: renesas: r9a09g077: Add xSPI core and module clocks	Lad Prabhakar	1	-3/+190
2025-12-15	clk: renesas: rzg2l: Select correct div round macro	Chris Brandt	1	-2/+2
2025-12-15	clk: renesas: rzg2l: Fix intin variable size	Chris Brandt	1	-1/+1
2025-12-08	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux	Linus Torvalds	12	-71/+1102
2025-11-24	clk: renesas: Use bitfield helpers	Geert Uytterhoeven	3	-19/+11
2025-11-13	clk: renesas: r9a09g077: Add SPI module clocks	Cosmin Tanislav	1	-1/+21
2025-11-13	clk: renesas: r9a09g056: Add USB3.0 clocks/resets	Lad Prabhakar	1	-1/+8
2025-11-13	clk: renesas: r9a09g057: Add USB3.0 clocks/resets	Lad Prabhakar	1	-1/+15
2025-11-13	clk: renesas: r9a09g047: Add RSCI clocks/resets	Biju Das	1	-0/+126
2025-11-12	clk: renesas: r9a06g032: Fix memory leak in error path	Haotian Zhang	1	-3/+3
2025-11-12	clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration	Lad Prabhakar	1	-14/+16
2025-11-12	clk: renesas: r9a09g077: Remove stray blank line	Lad Prabhakar	1	-1/+0
2025-11-12	clk: renesas: r9a09g077: Propagate rate changes to parent clocks	Lad Prabhakar	1	-2/+2