wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2023-07-27	clk: renesas: r8a7795: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2
2023-07-27	clk: renesas: emev2: Remove obsolete clkdev registration	Geert Uytterhoeven	1	-3/+0
2023-07-25	clk: renesas: r9a07g043: Add MTU3a clock and reset entry	Biju Das	1	-0/+3
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring	3	-4/+1
2023-07-11	clk: renesas: rzg2l: Simplify .determine_rate()	Christophe JAILLET	1	-7/+1
2023-07-10	clk: renesas: r9a09g011: Add CSI related clocks	Fabrizio Castro	1	-0/+15
2023-07-10	clk: renesas: r8a774b1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: r8a774e1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: r8a774a1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: rcar-gen3: Add support for ZG clock	Adam Ford	2	-4/+32
2023-06-26	Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-samsung' and 'clk-amlogic' into clk-next	Stephen Boyd	6	-49/+27
2023-06-08	clk: renesas: r9a06g032: Add a determine_rate hook	Maxime Ripard	1	-0/+1
2023-06-05	clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-11/+5
2023-06-05	clk: renesas: mstp: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-11/+7
2023-06-05	clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-20/+11
2023-05-23	clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write	Biju Das	2	-7/+2
2023-05-08	clk: renesas: r8a779a0: Add PWM clock	Wolfram Sang	1	-0/+1
2023-04-29	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux	Linus Torvalds	7	-204/+591
2023-04-13	clk: renesas: remove MODULE_LICENSE in non-modules	Nick Alcock	2	-2/+0
2023-03-30	clk: renesas: r8a77980: Add I2C5 clock	Nikita Yushchenko	1	-0/+1
2023-03-16	clk: renesas: Convert to platform remove callback returning void	Uwe Kleine-König	1	-4/+2
2023-03-10	clk: renesas: r9a06g032: Improve clock tables	Ralph Siemsen	1	-153/+407
2023-03-10	clk: renesas: r9a06g032: Document structs	Ralph Siemsen	1	-1/+49
2023-03-10	clk: renesas: r9a06g032: Drop unused fields	Ralph Siemsen	1	-5/+10
2023-03-10	clk: renesas: r9a06g032: Improve readability	Ralph Siemsen	1	-41/+80
2023-03-10	clk: renesas: r8a77980: Add Z2 clock	Geert Uytterhoeven	1	-0/+1
2023-03-10	clk: renesas: r8a77970: Add Z2 clock	Geert Uytterhoeven	1	-0/+1
2023-03-06	clk: renesas: r8a77995: Fix VIN parent clock	Geert Uytterhoeven	1	-1/+1
2023-03-06	clk: renesas: r8a77980: Add VIN clocks	Niklas Söderlund	1	-0/+16
2023-03-06	clk: renesas: r8a779g0: Add VIN clocks	Niklas Söderlund	1	-0/+16
2023-03-06	clk: renesas: r8a779g0: Add ISPCS clocks	Niklas Söderlund	1	-0/+2
2023-03-06	clk: renesas: r8a779g0: Add CSI-2 clocks	Niklas Söderlund	1	-0/+3
2023-03-06	clk: renesas: r8a779g0: Add thermal clock	Geert Uytterhoeven	1	-0/+1
2023-03-06	clk: renesas: r8a779g0: Add Audio clocks	Kuninori Morimoto	1	-0/+2
2023-03-06	clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H	Takeshi Kihara	1	-4/+4
2023-02-10	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	Wolfram Sang	5	-173/+13
2023-01-26	clk: renesas: r8a779g0: Add CAN-FD clocks	Geert Uytterhoeven	1	-0/+2
2023-01-26	clk: renesas: r8a779g0: Tidy up DMAC name on SYS-DMAC	Kuninori Morimoto	1	-2/+2
2023-01-26	clk: renesas: r8a779a0: Tidy up DMAC name on SYS-DMAC	Kuninori Morimoto	1	-2/+2
2023-01-24	clk: renesas: r8a779g0: Add custom clock for PLL2	Geert Uytterhoeven	3	-7/+164
2023-01-23	clk: renesas: cpg-mssr: Remove superfluous check in resume code	Geert Uytterhoeven	1	-3/+2
2023-01-23	clk: renesas: r9a06g032: Handle h2mode setting based on USBF presence	Herve Codina	1	-0/+28
2023-01-12	clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed	Alexey Khoroshilov	1	-1/+2
2023-01-12	clk: renesas: r9a07g044: Add clock and reset entries for CRU	Lad Prabhakar	1	-1/+25
2022-12-27	clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries	Phil Edworthy	1	-0/+20
2022-12-27	clk: renesas: r9a09g011: Add USB clock and reset entries	Biju Das	1	-0/+21
2022-12-27	clk: renesas: r9a09g011: Add TIM clock and reset entries	Biju Das	1	-0/+22
2022-12-26	clk: renesas: r8a779g0: Add display related clocks	Tomi Valkeinen	1	-0/+9
2022-12-26	clk: renesas: rcar-gen4: Restore PLL enum sort order	Geert Uytterhoeven	1	-1/+1
2022-12-26	clk: renesas: r8a779g0: Fix OSC predividers	Geert Uytterhoeven	1	-4/+4