diff options
| author |   Cong Dang <cong.dang.xn@renesas.com> | 2024-02-11 15:22:46 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-02-20 11:32:35 +0100 |
| commit | e89ea92f533b3f4d52c8778ca544a06078d0d6f0 (patch) | |
| tree | 20179e2bb69326c5c683ffd3473d95f3be48f59b /drivers/clk/renesas | |
| parent | clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable (diff) | |
| download | wireguard-linux-e89ea92f533b3f4d52c8778ca544a06078d0d6f0.tar.xz wireguard-linux-e89ea92f533b3f4d52c8778ca544a06078d0d6f0.zip | |
clk: renesas: r8a779h0: Add EtherAVB clocks
Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on
the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <cong.dang.xn@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a5b4252d9822ded3fd523bc35417306cae2ec2bd.1707661303.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a779h0-cpg-mssr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c index 70d104393594..46202e367d71 100644 --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c @@ -173,6 +173,9 @@ static const struct cpg_core_clk r8a779h0_core_clks[] = { }; static const struct mssr_mod_clk r8a779h0_mod_clks[] = { + DEF_MOD("avb0:rgmii0", 211, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("avb1:rgmii1", 212, R8A779H0_CLK_S0D8_HSC), + DEF_MOD("avb2:rgmii2", 213, R8A779H0_CLK_S0D8_HSC), DEF_MOD("hscif0", 514, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1), DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1), |