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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-07-17 15:11:21 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-07-27 14:32:46 +0200 |
| commit | fd177b9ac565423db6e0326445552735511e7dd1 (patch) | |
| tree | 7243fc17ecfdfc57e396c735cede69056093fcc7 /drivers/clk/renesas | |
| parent | clk: renesas: r8a7795: Add 3DGE and ZG support (diff) | |
| download | wireguard-linux-fd177b9ac565423db6e0326445552735511e7dd1.tar.xz wireguard-linux-fd177b9ac565423db6e0326445552735511e7dd1.zip | |
clk: renesas: r8a7796: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/291462bea7ffc13f8218c1901dc384b576bfc2d6.1689599217.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas')
| -rw-r--r-- | drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index c4969318508e..0bfd0771554f 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8), DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0), + DEF_GEN3_Z("zg", R8A7796_CLK_ZG, CLK_TYPE_GEN3_ZG, CLK_PLL4, 4, 24), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), @@ -130,6 +131,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { }; static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { + DEF_MOD("3dge", 112, R8A7796_CLK_ZG), DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6), DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2), |