diff options
| author |   Jernej Skrabec <jernej.skrabec@gmail.com> | 2022-09-28 22:01:22 +0200 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-09-28 16:42:51 -0700 |
| commit | 4014e916fd0cea19b559890588d70b4e9f44b87f (patch) | |
| tree | 1f394675f1aaade0555ee43c1848cf33d2983c40 /drivers/clk/sunxi-ng | |
| parent | clk: imx: imx6sx: remove the SET_RATE_PARENT flag for QSPI clocks (diff) | |
| download | wireguard-linux-4014e916fd0cea19b559890588d70b4e9f44b87f.tar.xz wireguard-linux-4014e916fd0cea19b559890588d70b4e9f44b87f.zip | |
clk: sunxi-ng: h6: Fix default PLL GPU rate
In commit 4167ac8a657e ("clk: sunxi-ng: sun50i: h6: Modify GPU clock
configuration to support DFS") divider M0 was forced to be 1 in order to
support DFS. However, that left N as it is, at high value of 36. On
boards without devfreq enabled (all of them in kernel 6.0), this
effectively sets GPU frequency to 864 MHz. This is about 100 MHz above
maximum supported frequency.
In order to fix this, let's set N to 18 (register value 17). That way
default frequency of 432 MHz is preserved.
Fixes: 4167ac8a657e ("clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20220928200122.3963509-1-jernej.skrabec@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/sunxi-ng')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index 30056da3e0af..42568c616181 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -1191,9 +1191,13 @@ static int sun50i_h6_ccu_probe(struct platform_device *pdev) if (IS_ERR(reg)) return PTR_ERR(reg); - /* Force PLL_GPU output divider bits to 0 */ + /* + * Force PLL_GPU output divider bits to 0 and adjust + * multiplier to sensible default value of 432 MHz. + */ val = readl(reg + SUN50I_H6_PLL_GPU_REG); - val &= ~BIT(0); + val &= ~(GENMASK(15, 8) | BIT(0)); + val |= 17 << 8; writel(val, reg + SUN50I_H6_PLL_GPU_REG); /* Force GPU_CLK divider bits to 0 */ |