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path: root/drivers/clk/sunxi-ng (follow)
AgeCommit message (Expand)AuthorFilesLines
2023-11-18clk: sunxi-ng: nkm: remove redundant initialization of tmp_parentColin Ian King1-3/+2
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-nextStephen Boyd10-55/+205
2023-08-09clk: sunxi-ng: nkm: Prefer current parent rateFrank Oltmanns1-1/+2
2023-08-09clk: sunxi-ng: a64: select closest rate for pll-video0Frank Oltmanns1-22/+16
2023-08-09clk: sunxi-ng: div: Support finding closest rateFrank Oltmanns1-0/+30
2023-08-09clk: sunxi-ng: mux: Support finding closest rateFrank Oltmanns2-12/+39
2023-08-09clk: sunxi-ng: nkm: Support finding closest rateFrank Oltmanns2-12/+10
2023-08-09clk: sunxi-ng: nm: Support finding closest rateFrank Oltmanns2-11/+50
2023-08-09clk: sunxi-ng: Add helper function to find closest rateFrank Oltmanns2-0/+17
2023-08-09clk: sunxi-ng: Add feature to find closest rateFrank Oltmanns1-0/+1
2023-08-09clk: sunxi-ng: a64: allow pll-mipi to set parent's rateFrank Oltmanns1-1/+2
2023-08-09clk: sunxi-ng: nkm: consider alternative parent rates when determining rateFrank Oltmanns1-1/+43
2023-08-09clk: sunxi-ng: nkm: Use correct parameter name for parent HWFrank Oltmanns1-1/+1
2023-07-31clk: sunxi-ng: Modify mismatched function nameZhang Jianhua1-1/+1
2023-07-19clk: Explicitly include correct DT includesRob Herring7-6/+8
2023-05-18clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 muxRoman Beranek1-1/+13
2023-01-08clk: sunxi-ng: d1: Add CAN bus gates and resetsFabien Poussin2-1/+12
2023-01-08clk: sunxi-ng: d1: Mark cpux clock as criticalAndrás Szemző1-1/+1
2023-01-08clk: sunxi-ng: d1: Allow building for R528/T113Samuel Holland1-4/+4
2023-01-08clk: sunxi-ng: Move SoC driver conditions to dependenciesSamuel Holland1-22/+24
2023-01-08clk: sunxi-ng: Remove duplicate ARCH_SUNXI dependenciesSamuel Holland1-22/+21
2023-01-08clk: sunxi-ng: Avoid computing the rate twiceSamuel Holland5-23/+26
2023-01-08clk: sunxi-ng: h3/h5: Model H3 CLK_DRAM as a fixed clockSamuel Holland1-5/+10
2023-01-08clk: sunxi-ng: fix ccu_mmc_timing.c kernel-doc issuesRandy Dunlap1-4/+4
2022-11-16clk: sunxi-ng: f1c100s: Add IR mod clockAndre Przywara2-2/+11
2022-11-16clk: sunxi-ng: v3s: Correct the header guard of ccu-sun8i-v3s.hWei Li1-3/+3
2022-10-08Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds4-38/+26
2022-09-28clk: sunxi-ng: h6: Fix default PLL GPU rateJernej Skrabec1-2/+6
2022-09-08clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helperYang Yingliang1-6/+3
2022-09-08clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helperYang Yingliang1-13/+6
2022-09-08clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helperYang Yingliang1-19/+9
2022-08-25clk: sunxi-ng: d1: Limit PLL rates to stable rangesSamuel Holland1-0/+8
2022-07-08clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFSRoman Stratiienko1-3/+13
2022-06-06clk: sunxi-ng: Deduplicate ccu_clks arraysSamuel Holland5-289/+37
2022-05-27Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds4-2/+15
2022-05-17Revert "clk: sunxi-ng: sun6i-rtc: Add support for H6"Jernej Skrabec1-15/+0
2022-05-06clk: sunxi-ng: h616: Add PLL derived 32KHz clockAndre Przywara2-1/+9
2022-05-06clk: sunxi-ng: h6-r: Add RTC gate clockAndre Przywara2-1/+6
2022-04-24clk: sunxi-ng: sun6i-rtc: Mark rtc-32k as criticalSamuel Holland1-0/+1
2022-04-06clk: sunxi-ng: fix not NULL terminated coccicheck errorWan Jiabing1-0/+1
2022-03-25clk: sunxi-ng: sun6i-rtc: include clk/sunxi-ng.hAlexandre Belloni1-0/+2
2022-03-23clk: sunxi-ng: sun6i-rtc: Add support for H6Samuel Holland1-0/+15
2022-03-23clk: sunxi-ng: Add support for the sun6i RTC clocksSamuel Holland4-0/+400
2022-03-23clk: sunxi-ng: mux: Allow muxes to have keysSamuel Holland2-0/+8
2022-01-12Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linuxLinus Torvalds44-237/+2256
2021-11-23dt-bindings: clock: sunxi: Export CLK_DRAM for devfreqSamuel Holland2-4/+0
2021-11-23clk: sunxi-ng: Add support for the D1 SoC clocksSamuel Holland6-0/+1576
2021-11-23clk: sunxi-ng: gate: Add macros for gates with fixed dividersSamuel Holland1-1/+31
2021-11-23clk: sunxi-ng: mux: Add macros using clk_parent_data and clk_hwSamuel Holland1-0/+33
2021-11-23clk: sunxi-ng: mp: Add macros using clk_parent_data and clk_hwSamuel Holland1-0/+49