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| author |   Rhyland Klein <rklein@nvidia.com> | 2015-06-18 17:28:24 -0400 |
|---|---|---|
| committer |   Thierry Reding <treding@nvidia.com> | 2015-11-20 18:05:02 +0100 |
| commit | d907f4b4a178b7bbc8edc67191f63155d6492b80 (patch) | |
| tree | e093ac8890fd72923b6d33ffb4a88357c2182c64 /drivers/clk/tegra/clk.h | |
| parent | clk: tegra: pll: Don't unconditionally set LOCK flags (diff) | |
| download | wireguard-linux-d907f4b4a178b7bbc8edc67191f63155d6492b80.tar.xz wireguard-linux-d907f4b4a178b7bbc8edc67191f63155d6492b80.zip | |
clk: tegra: pll: Add logic for handling SDM data
This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.
The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/clk/tegra/clk.h')
| -rw-r--r-- | drivers/clk/tegra/clk.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index 488ee677e15b..72368e1ed46a 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -110,14 +110,16 @@ struct clk *tegra_clk_register_mc(const char *name, const char *parent_name, * @m: input divider * @p: post divider * @cpcon: charge pump current + * @sdm_data: fraction divider setting (0 = disabled) */ struct tegra_clk_pll_freq_table { unsigned long input_rate; unsigned long output_rate; - u16 n; + u32 n; u16 m; u8 p; u8 cpcon; + u16 sdm_data; }; /** @@ -174,6 +176,10 @@ struct div_nmp { * @lock_enable_bit_idx: Bit index to enable PLL lock * @iddq_reg: PLL IDDQ register offset * @iddq_bit_idx: Bit index to enable PLL IDDQ + * @sdm_din_reg: Register offset where SDM settings are + * @sdm_din_mask: Mask of SDM divider bits + * @sdm_ctrl_reg: Register offset where SDM enable is + * @sdm_ctrl_en_mask: Mask of SDM enable bit * @aux_reg: AUX register offset * @dyn_ramp_reg: Dynamic ramp control register offset * @ext_misc_reg: Miscellaneous control register offsets @@ -188,6 +194,8 @@ struct div_nmp { * @div_nmp: offsets and widths on n, m and p fields * @freq_table: array of frequencies supported by PLL * @fixed_rate: PLL rate if it is fixed + * @set_gain: Callback to adjust N div for SDM enabled + * PLL's based on fractional divider value. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for @@ -225,6 +233,10 @@ struct tegra_clk_pll_params { u32 lock_enable_bit_idx; u32 iddq_reg; u32 iddq_bit_idx; + u32 sdm_din_reg; + u32 sdm_din_mask; + u32 sdm_ctrl_reg; + u32 sdm_ctrl_en_mask; u32 aux_reg; u32 dyn_ramp_reg; u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT]; @@ -239,6 +251,7 @@ struct tegra_clk_pll_params { struct div_nmp *div_nmp; struct tegra_clk_pll_freq_table *freq_table; unsigned long fixed_rate; + void (*set_gain)(struct tegra_clk_pll_freq_table *cfg); }; #define TEGRA_PLL_USE_LOCK BIT(0) |