diff options
| author |   Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 2022-02-22 18:39:03 +0530 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@kernel.org> | 2022-03-29 10:17:49 -0700 |
| commit | a6aa462c3efc144808b0cf8a0fe993d4fe2c079a (patch) | |
| tree | 9e4ac23aa71109930d0a79d3475f72064b0bea65 /drivers/clk/zynq/clkc.c | |
| parent | clk: zynq: trivial warning fix (diff) | |
| download | wireguard-linux-a6aa462c3efc144808b0cf8a0fe993d4fe2c079a.tar.xz wireguard-linux-a6aa462c3efc144808b0cf8a0fe993d4fe2c079a.zip | |
clk: zynq: Update the parameters to zynq_clk_register_periph_clk
In case there are only one gate or the two_gate is 0 the clk1 clock
passed is not used. We are passing 0 which is arm_pll.
Pass a invalid clock instead.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/20220222130903.17235-3-shubhrajyoti.datta@xilinx.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/zynq/clkc.c')
| -rw-r--r-- | drivers/clk/zynq/clkc.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c index 434511dcf5cb..7bdeaff2bfd6 100644 --- a/drivers/clk/zynq/clkc.c +++ b/drivers/clk/zynq/clkc.c @@ -355,14 +355,14 @@ static void __init zynq_clk_setup(struct device_node *np) periph_parents, enable); } - zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, - SLCR_LQSPI_CLK_CTRL, periph_parents, 0); + zynq_clk_register_periph_clk(lqspi, clk_max, clk_output_name[lqspi], NULL, + SLCR_LQSPI_CLK_CTRL, periph_parents, 0); - zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, - SLCR_SMC_CLK_CTRL, periph_parents, 0); + zynq_clk_register_periph_clk(smc, clk_max, clk_output_name[smc], NULL, + SLCR_SMC_CLK_CTRL, periph_parents, 0); - zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, - SLCR_PCAP_CLK_CTRL, periph_parents, 0); + zynq_clk_register_periph_clk(pcap, clk_max, clk_output_name[pcap], NULL, + SLCR_PCAP_CLK_CTRL, periph_parents, 0); zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, |