wireguard-linux - WireGuard for the Linux kernel

Age	Commit message (Expand)	Author	Files	Lines
2024-03-08	clk: zynq: Prevent null pointer dereference caused by kmalloc failure	Duoming Zhou	1	-5/+3
2022-03-29	clk: zynq: Update the parameters to zynq_clk_register_periph_clk	Shubhrajyoti Datta	1	-6/+6
2022-03-29	clk: zynq: trivial warning fix	Shubhrajyoti Datta	1	-0/+1
2021-02-11	clk: zynq: clkc: Remove various instances of an unused variable 'clk'	Lee Jones	1	-38/+35
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 401	Thomas Gleixner	1	-12/+1
2019-04-23	clk: core: replace clk_{readl,writel} with {readl,writel}	Jonas Gorski	1	-3/+3
2018-08-30	clk: Convert to using %pOFn instead of device_node.name	Rob Herring	1	-2/+2
2016-03-02	clk: zynq: Remove CLK_IS_ROOT	Stephen Boyd	1	-2/+1
2015-07-20	clk: zynq: Include clk.h	Stephen Boyd	1	-0/+1
2015-06-04	clk: make several parent names const	Uwe Kleine-König	1	-9/+16
2015-04-12	clk: don't use __initconst for non-const arrays	Uwe Kleine-König	1	-12/+12
2015-01-27	clk: zynq: Force CPU_2X clock to be ungated	Soren Brinkmann	1	-0/+1
2014-09-09	clk: zynq: Move const initdata into correct code section	Soren Brinkmann	1	-15/+14
2014-09-09	clk: zynq: Remove pointless return at end of void function	Soren Brinkmann	1	-1/+0
2014-04-22	clk: zynq: Leave debug clocks in bootup state	Soren Brinkmann	1	-0/+12
2014-04-05	Merge tag 'clk-for-linus-3.15' of git://git.linaro.org/people/mike.turquette/linux	Linus Torvalds	1	-2/+2
2014-03-17	ARM: zynq: Move of_clk_init from clock driver	Michal Simek	1	-2/+0
2014-02-25	clk: zynq: Use clk_readl/clk_writel helper function	Michal Simek	1	-2/+2
2014-02-10	ARM: zynq: Map I/O memory on clkc init	Michal Simek	1	-26/+63
2013-12-20	clk/zynq/clkc: Add 'fclk-enable' feature	Soren Brinkmann	1	-3/+15
2013-10-07	clk/zynq: Fix possible memory leak	Felipe Pena	1	-1/+15
2013-09-09	Merge tag 'clk-for-linus-3.12' of git://git.linaro.org/people/mturquette/linux	Linus Torvalds	1	-34/+48
2013-08-19	clk: add CLK_SET_RATE_NO_REPARENT flag	James Hogan	1	-36/+50
2013-08-13	clk/zynq/clkc: Add CLK_SET_RATE_PARENT flag to ethernet muxes	Soren Brinkmann	1	-4/+6
2013-08-13	clk/zynq/clkc: Add dedicated spinlock for the SWDT	Soren Brinkmann	1	-1/+2
2013-05-27	clk: zynq: Add clock controller driver	Soren Brinkmann	1	-0/+533