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| author |   Stephen Boyd <sboyd@kernel.org> | 2019-03-08 10:29:30 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-03-08 10:29:30 -0800 |
| commit | efb1e0b07139974b506c90f4e0621d5866ee48b7 (patch) | |
| tree | 2f320c3eefa309610aa1f6223f51ec682196f56c /drivers/clk | |
| parent | Merge branches 'clk-qcom-msm8998', 'clk-fractional-parent', 'clk-x86-mv' and 'clk-SA-fixes' into clk-next (diff) | |
| parent | clk: ingenic: Remove set but not used variable 'enable' (diff) | |
| parent | clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel (diff) | |
| parent | clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks (diff) | |
| parent | clk: mediatek: Mark bus and DRAM related clocks as critical (diff) | |
| parent | clk: mediatek: correct cpu clock name for MT8173 SoC (diff) | |
| download | wireguard-linux-efb1e0b07139974b506c90f4e0621d5866ee48b7.tar.xz wireguard-linux-efb1e0b07139974b506c90f4e0621d5866ee48b7.zip | |
Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next
* clk-ingenic:
clk: ingenic: Remove set but not used variable 'enable'
clk: ingenic: Fix doc of ingenic_cgu_div_info
clk: ingenic: Fix round_rate misbehaving with non-integer dividers
clk: ingenic: jz4740: Fix gating of UDC clock
* clk-mtk-mux:
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
clk: mediatek: add MUX_GATE_FLAGS_2
* clk-qcom-sdm845-pcie:
clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks
* clk-mtk-crit:
clk: mediatek: Mark bus and DRAM related clocks as critical
clk: mediatek: Add flags to mtk_gate
clk: mediatek: Add MUX_FLAGS macro
* clk-mtk:
clk: mediatek: correct cpu clock name for MT8173 SoC