diff options
| author |   Wesley Chalmers <Wesley.Chalmers@amd.com> | 2023-05-31 13:29:34 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2023-07-10 09:02:07 -0400 |
| commit | 3b6df06f01cdbff3b610b492ad4879691afdc70d (patch) | |
| tree | 2174a5d47821db18916bcbb6c2ad45de9881da9d /drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | |
| parent | drm/amd/display: Do not set drr on pipe commit (diff) | |
| download | wireguard-linux-3b6df06f01cdbff3b610b492ad4879691afdc70d.tar.xz wireguard-linux-3b6df06f01cdbff3b610b492ad4879691afdc70d.zip | |
drm/amd/display: Block optimize on consecutive FAMS enables
[WHY]
It is possible to commit state multiple times in rapid succession with
FAMS enabled; if each of these commits were to set optimized_required,
then the user may see latency.
[HOW]
fw_based_mclk_switching is currently not used in dc->clk_mgr; use it
to track whether the current state has FAMS enabled;
if it has, then do not disable FAMS in prepare_bandwidth, and do not set
optimized_required.
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index dba7eab9a2c4..5cfa37804d7c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -2127,6 +2127,9 @@ void dcn20_optimize_bandwidth( dc_dmub_srv_p_state_delegate(dc, true, context); context->bw_ctx.bw.dcn.clk.p_state_change_support = true; + dc->clk_mgr->clks.fw_based_mclk_switching = true; + } else { + dc->clk_mgr->clks.fw_based_mclk_switching = false; } dc->clk_mgr->funcs->update_clocks( |