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| author |   Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> | 2020-06-01 20:30:58 +0300 |
|---|---|---|
| committer |   Manasi Navare <manasi.d.navare@intel.com> | 2020-06-04 11:11:56 -0700 |
| commit | 19aefbc778b8b8e87c2d31be9736c634f0ea95a8 (patch) | |
| tree | 2d5d29329515bde0864e2575fea7c1e8830c4385 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915/rkl: Handle comp master/slave relationships for PHYs (diff) | |
| download | wireguard-linux-19aefbc778b8b8e87c2d31be9736c634f0ea95a8.tar.xz wireguard-linux-19aefbc778b8b8e87c2d31be9736c634f0ea95a8.zip | |
drm/i915: Fix wrong CDCLK adjustment changes
Previous patch didn't take into account all pipes
but only those in state, which could cause wrong
CDCLK conclcusions and calculations.
Also there was a severe issue with min_cdclk being
assigned to 0 every compare cycle.
Too bad this was found by me only after merge.
This could be also causing the issues in test, however
not clear - anyway marking this as fixing the
"Adjust CDCLK accordingly to our DBuf bw needs".
v2: - s/pipe/crtc->pipe/
- save a bit of instructions by
skipping inactive pipes, without
getting 0 DBuf slice mask for it.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Fixes: cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200601173058.5084-1-stanislav.lisovskiy@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions