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| author |   José Roberto de Souza <jose.souza@intel.com> | 2020-06-02 13:54:24 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-06-04 13:36:40 -0700 |
| commit | 9fa6769952ee14250bb7107a2ec66062d2ccae1e (patch) | |
| tree | bf82c0453ffb414b6a416891d0077e4f99e9f389 /drivers/gpu/drm/i915/display/intel_dp_mst.c | |
| parent | drm/i915: Fix wrong CDCLK adjustment changes (diff) | |
| download | wireguard-linux-9fa6769952ee14250bb7107a2ec66062d2ccae1e.tar.xz wireguard-linux-9fa6769952ee14250bb7107a2ec66062d2ccae1e.zip | |
drm/i915/tgl: Add HBR and HBR2+ voltage swing table
As latest update we have now 2 voltage swing tables for DP over DKL
PHY with only one difference in Level 0 pre-emphasis 3.
So with 2 tables for DP is time to have one single function to return
all DKL voltage swing tables.
BSpec: 49292
Cc: Khaled Almahallawy <khaled.almahallawy@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
Reviewed-by: Khaled Almahallawy<khaled.almahallawy@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200602205424.138143-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions