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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-12-02 15:44:11 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-12-08 21:33:52 +0200 |
| commit | 0504d0acc282fe99cf4bd0cdc5551b352357142f (patch) | |
| tree | a0a996a9f98e11025d0c32f57ee2dffd08a84d6f /drivers/gpu/drm/i915/display/intel_panel.c | |
| parent | drm/i915/vrr: Fix guardband/vblank exit length calculation for adl+ (diff) | |
| download | wireguard-linux-0504d0acc282fe99cf4bd0cdc5551b352357142f.tar.xz wireguard-linux-0504d0acc282fe99cf4bd0cdc5551b352357142f.zip | |
drm/i915/vrr: Reorder transcoder vs. vrr enable/disable
On mtl it looks like disabling VRR after the transcoder has
been disabled can cause the pipe/transcoder to get stuck
when re-enabled in non-vrr mode. Reversing the order seems to
help.
Bspec is extremely confused about the VRR enable/disable sequence
anyway, and this now more closely matches the non-modeset VRR
sequence, whereas the full modeset sequence still claims that
the original order is fine. But since we eventually want to toggle
VRR without a full modeset anyway this seems like the better order
to follow.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221202134412.21943-4-ville.syrjala@linux.intel.com
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_panel.c')
0 files changed, 0 insertions, 0 deletions