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| author |   Imre Deak <imre.deak@intel.com> | 2022-02-22 18:51:31 +0200 |
|---|---|---|
| committer | Imre Deak <imre.deak@intel.com> | 2022-02-28 17:03:32 +0200 |
| commit | 359441cdc5e7f872f3c53757606cdd6bd6b842df (patch) | |
| tree | 5c1c579bfb2cad3b315e1d77379733692c15c9ca /drivers/gpu/drm/i915/intel_pm.c | |
| parent | drm/i915: Fix the VDSC_PW2 power domain enum value (diff) | |
| download | wireguard-linux-359441cdc5e7f872f3c53757606cdd6bd6b842df.tar.xz wireguard-linux-359441cdc5e7f872f3c53757606cdd6bd6b842df.zip | |
drm/i915: Sanitize open-coded power well enable()/disable() calls
Instead of open-coding the call of the power wells' enable()/disable()
hooks use the corresponding helper functions. This will also ensure that
the power well's cached-enable state is always up-to-date. Luckily the
lack of this updating hasn't been a problem, since the state either
didn't change (in intel_display_power_set_target_dc_state()), or got
updated subsequently (for vlv_cmnlane_wa(), in the following
intel_power_domains_sync_hw()).
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220222165137.1004194-3-imre.deak@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
0 files changed, 0 insertions, 0 deletions