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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-03-31 14:11:54 +0300 |
|---|---|---|
| committer |   Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-31 17:28:43 +0200 |
| commit | b37a6434cfa9477e6e5cb386e7e3d135073aef63 (patch) | |
| tree | f3b8094c5472d3e7093c3bd39eaddc22129bbc84 /drivers/gpu/drm/i915/intel_sdvo.c | |
| parent | drm/i915: Return more precise cdclk for gen2/3 (diff) | |
| download | wireguard-linux-b37a6434cfa9477e6e5cb386e7e3d135073aef63.tar.xz wireguard-linux-b37a6434cfa9477e6e5cb386e7e3d135073aef63.zip | |
drm/i915: ILK cdclk seems to be 450MHz
Based on the BIOS DP A AUX 2x clock divider the cdclk frequency
on ILK is 450Mhz. At least that holds on my ILK and it matches
how we program the divider.
Supposedly cdclk is 400MHz on SNB and IVB, again based on the AUX 2x
clock divider. Note that I don't have a SNB or IVB machine with
eDP so I couldn't verify what the BIOS used, so this notion is
purely based on our current code,
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sdvo.c')
0 files changed, 0 insertions, 0 deletions