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author | Andre Przywara <andre.przywara@arm.com> | 2020-03-24 13:23:46 +0000 |
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committer | David S. Miller <davem@davemloft.net> | 2020-03-24 16:33:05 -0700 |
commit | f735c40ed93ccaeb52d026def47ac1a423df7133 (patch) | |
tree | e0610802bfd95e433f3c742261d4acdd6b5a7a0a /drivers/net/ethernet/xilinx/xilinx_axienet.h | |
parent | net: axienet: Upgrade descriptors to hold 64-bit addresses (diff) | |
download | wireguard-linux-f735c40ed93ccaeb52d026def47ac1a423df7133.tar.xz wireguard-linux-f735c40ed93ccaeb52d026def47ac1a423df7133.zip |
net: axienet: Autodetect 64-bit DMA capability
When newer revisions of the Axienet IP are configured for a 64-bit bus,
we *need* to write to the MSB part of the an address registers,
otherwise the IP won't recognise this as a DMA start condition.
This is even true when the actual DMA address comes from the lower 4 GB.
To autodetect this configuration, at probe time we write all 1's to such
an MSB register, and see if any bits stick. If this is configured for a
32-bit bus, those MSB registers are RES0, so reading back 0 indicates
that no MSB writes are necessary.
On the other hands reading anything other than 0 indicated the need to
write the MSB registers, so we set the respective flag.
The actual DMA mask stays at 32-bit for now. To help bisecting, a
separate patch will enable allocations from higher addresses.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/xilinx/xilinx_axienet.h')
-rw-r--r-- | drivers/net/ethernet/xilinx/xilinx_axienet.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet.h b/drivers/net/ethernet/xilinx/xilinx_axienet.h index 84c4c3655516..fbaf3c987d9c 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet.h +++ b/drivers/net/ethernet/xilinx/xilinx_axienet.h @@ -161,6 +161,7 @@ #define XAE_FCC_OFFSET 0x0000040C /* Flow Control Configuration */ #define XAE_EMMC_OFFSET 0x00000410 /* EMAC mode configuration */ #define XAE_PHYC_OFFSET 0x00000414 /* RGMII/SGMII configuration */ +#define XAE_ID_OFFSET 0x000004F8 /* Identification register */ #define XAE_MDIO_MC_OFFSET 0x00000500 /* MII Management Config */ #define XAE_MDIO_MCR_OFFSET 0x00000504 /* MII Management Control */ #define XAE_MDIO_MWD_OFFSET 0x00000508 /* MII Management Write Data */ |