diff options
| author |   Gustavo Sousa <gustavo.sousa@intel.com> | 2026-05-14 18:44:45 -0300 |
|---|---|---|
| committer |   Rodrigo Vivi <rodrigo.vivi@intel.com> | 2026-05-18 09:22:41 -0400 |
| commit | a4660bd949733fd6ea621fdb50fabac2608155e9 (patch) | |
| tree | 176c50ab025bba4fffdb22cd5bedcafbee7561cb /include/linux/bcma/ssh:/git@git.zx2c4.com | |
| parent | drm/xe: Define CACHE_MODE_1 as MCR register (diff) | |
drm/xe: Define and use MCR version of COMMON_SLICE_CHICKEN1
The register COMMON_SLICE_CHICKEN1 is a MCR register on Xe2.
Let's make sure to define a MCR version of it and use it for the
relevant IP versions.
Use XEHP_ as prefix for the register name, since it is MCR as of Xe_HP.
Fixes: a5d221924e13 ("drm/xe/xe2_hpg: Add set of workarounds")
Fixes: 9f18b55b6d3f ("drm/xe/xe2: Add workaround 18033852989")
Bspec: 66534, 71185
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260514-rtp-mcr-check-v3-2-30dd47855fee@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
(cherry picked from commit a672725fdbfc3ea430130039d677c7dc98d59df8)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'include/linux/bcma/ssh:/git@git.zx2c4.com')
0 files changed, 0 insertions, 0 deletions