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| author |   Ian Munsie <imunsie@au1.ibm.com> | 2016-07-14 07:17:02 +1000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2016-07-14 20:26:35 +1000 |
| commit | 48b3adf33459c1c42766d9c2068a592216fe7812 (patch) | |
| tree | 315d6af3ce690bcace65d8ad10a84868f888e1f9 /include/misc | |
| parent | cxl: Add cxl_slot_is_supported API (diff) | |
| download | wireguard-linux-48b3adf33459c1c42766d9c2068a592216fe7812.tar.xz wireguard-linux-48b3adf33459c1c42766d9c2068a592216fe7812.zip | |
cxl: Enable bus mastering for devices using CAPP DMA mode
Devices that use CAPP DMA mode (such as the Mellanox CX4) require bus
master to be enabled in order for the CAPI traffic to flow. This should
be harmless to enable for other cxl devices, so unconditionally enable
it in the adapter init flow.
Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'include/misc')
0 files changed, 0 insertions, 0 deletions