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| author |   Fabrizio Castro <fabrizio.castro.jz@renesas.com> | 2024-09-30 15:52:42 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-10-07 10:33:51 +0200 |
| commit | 44d13e198cbf031fdb8cb20b6bbbe82adcb951ca (patch) | |
| tree | 7bf2ca6ba954c598aa4776edad5309cb57a05ddf /scripts/gdb/linux/modules.py | |
| parent | clk: renesas: r9a09g057: Add CA55 core clocks (diff) | |
| download | wireguard-linux-44d13e198cbf031fdb8cb20b6bbbe82adcb951ca.tar.xz wireguard-linux-44d13e198cbf031fdb8cb20b6bbbe82adcb951ca.zip | |
clk: renesas: r9a09g057: Add clock and reset entries for ICU
Add clock and reset entries for the Renesas RZ/V2H(P) ICU IP block.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240930145244.356565-4-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'scripts/gdb/linux/modules.py')
0 files changed, 0 insertions, 0 deletions