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| author |   Icenowy Zheng <icenowy@aosc.io> | 2019-07-28 11:12:24 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime.ripard@bootlin.com> | 2019-08-12 10:05:48 +0200 |
| commit | 0ed4c252bf80b35fe768ec6506b2e58986f99687 (patch) | |
| tree | 8f831412d9c6a5cbd64d582e63f9e5a37adf1e96 /scripts/gdb/linux/utils.py | |
| parent | clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks (diff) | |
| download | wireguard-linux-0ed4c252bf80b35fe768ec6506b2e58986f99687.tar.xz wireguard-linux-0ed4c252bf80b35fe768ec6506b2e58986f99687.zip | |
clk: sunxi-ng: v3s: add Allwinner V3 support
Allwinner V3 has the same main die with V3s, but with more pins wired.
There's a I2S bus on V3 that is not available on V3s.
Add the V3-only peripheral's clocks and reset to the V3s CCU driver,
bound to a new V3 compatible string. The driver name is not changed
because it's part of the device tree binding (the header file name).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions