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| author |   Anson Huang <Anson.Huang@nxp.com> | 2019-08-18 02:32:23 -0400 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2019-08-19 15:36:58 +0200 |
| commit | 313ccbad732dfcede65cbbb7444c00f20c08f766 (patch) | |
| tree | e3ace710bd632b453ddcf6b737fca4720e3676ad /scripts/gdb/linux/utils.py | |
| parent | clk: imx8mn: fix int pll clk gate (diff) | |
| download | wireguard-linux-313ccbad732dfcede65cbbb7444c00f20c08f766.tar.xz wireguard-linux-313ccbad732dfcede65cbbb7444c00f20c08f766.zip | |
clk: imx8mn: Add missing rate_count assignment for each PLL structure
Add .rate_count assignment which is necessary for searching required
PLL rate from the each PLL table.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions