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| author |   Vignesh Raghavendra <vigneshr@ti.com> | 2021-05-11 20:49:55 +0530 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2021-05-20 17:16:55 +0200 |
| commit | 31fae7c8b18c3f8029a2a5dce97a3182c1a167a0 (patch) | |
| tree | bc4e8a7216e6de1eedde30285a382ac025ca2ccc /scripts/gdb/linux/utils.py | |
| parent | serial: 8250: Use BIT(x) for UART_{CAP,BUG}_* (diff) | |
| download | wireguard-linux-31fae7c8b18c3f8029a2a5dce97a3182c1a167a0.tar.xz wireguard-linux-31fae7c8b18c3f8029a2a5dce97a3182c1a167a0.zip | |
serial: 8250: 8250_omap: Fix possible interrupt storm
It is possible that RX TIMEOUT is signalled after RX FIFO has been
drained, in which case a dummy read of RX FIFO is required to clear RX
TIMEOUT condition. Otherwise, RX TIMEOUT condition is not cleared
leading to an interrupt storm
Cc: stable@vger.kernel.org
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210511151955.28071-1-vigneshr@ti.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions