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| author |   Anson Huang <Anson.Huang@nxp.com> | 2019-08-18 02:32:24 -0400 |
|---|---|---|
| committer |   Shawn Guo <shawnguo@kernel.org> | 2019-08-19 15:38:55 +0200 |
| commit | 613cc5cd745c77da2b9090bcb29f82c05b853567 (patch) | |
| tree | d67dd0ca9dddfdaa0c772dea84f8198f3300af69 /scripts/gdb/linux/utils.py | |
| parent | clk: imx8mn: Add missing rate_count assignment for each PLL structure (diff) | |
| download | wireguard-linux-613cc5cd745c77da2b9090bcb29f82c05b853567.tar.xz wireguard-linux-613cc5cd745c77da2b9090bcb29f82c05b853567.zip | |
clk: imx8mn: Add necessary frequency support for ARM PLL table
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions